公开(公告)号：US11329063B2

公开(公告)日：2022-05-10

申请号：US16848035

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L27/1157 ,  H01L21/28

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US12048158B2

公开(公告)日：2024-07-23

申请号：US17722736

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bio Kim ,  Yujin Kim ,  Philouk Nam ,  Youngseon Son ,  Kyongwon An ,  Jumi Yun ,  Woojin Jang

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/02249 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A vertical memory device includes a channel extending in a vertical direction on a substrate, a charge storage structure on an outer sidewall of the channel and including a tunnel insulation pattern, a charge trapping pattern, and a first blocking pattern sequentially stacked in a horizontal direction, and gate electrodes spaced apart from each other in the vertical direction, each of which surrounds the charge storage structure. The charge storage structure includes charge trapping patterns, each of which faces one of the gate electrodes in the horizontal direction. A length in the vertical direction of an inner sidewall of each of the charge trapping patterns facing the tunnel insulation pattern is less than a length in the vertical direction of an outer sidewall thereof facing the first blocking pattern.

公开(公告)号：US20230380164A1

公开(公告)日：2023-11-23

申请号：US18116434

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeonghoon Park ,  Inhwan Baek ,  Jaebok Baek ,  Jeehoon Han ,  Seungyoon Kim ,  Heesuk Kim ,  Byoungjae Park ,  Jongseon Ahn ,  Jumi Yun

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first semiconductor structure including a first substrate, circuit devices on the first substrate, and a lower interconnection structure connected to the circuit devices; and a second semiconductor structure on the first semiconductor structure. The second semiconductor structure may include: a second substrate having a first region and a second region; a substrate insulating layer extending through the second substrate; a landing pad extending through the substrate insulating layer; gate electrodes, each having a gate pad region on the second region having an exposed upper surface; and a gate contact plug extending through the gate pad region of at least one of the gate electrodes and into the landing pad. The landing pad may include a pad portion that is surrounded by an internal side surface of the substrate insulating layer, and a via portion extending from the pad portion to the lower interconnection structure.