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1.发明申请METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE AND CHEMICAL VAPOR DEPOSITION APPARATUS 审中-公开制造半导体发光装置和化学蒸气沉积装置的方法公开(公告)号：US20140235007A1
公开(公告)日：2014-08-21
申请号：US14146477
申请日：2014-01-02
发明人： Sang Heon HAN , Nam Sung KIM , Dong Joon KIM , Kong Tan SA , Tong Ik SHIN , Do Young RHEE , Jeong Wook LEE
IPC分类号： H01L33/00 , H01L21/673
CPC分类号： H01L33/007 , C23C16/4583 , C23C16/54 , H01L21/0237 , H01L21/0242 , H01L21/02433 , H01L21/0254 , H01L21/02576 , H01L21/0262 , H01L21/67326 , H01L21/68735 , H01L21/68764 , H01L21/68771 , H01L33/32
摘要： A method of manufacturing a semiconductor light emitting device, includes sequentially growing a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a substrate to form a light emitting layer. The forming of the light emitting layer includes a first growth process, a second growth process and a transfer process. The first growth process uses a first susceptor having a mounting surface with a first curvature. The second growth process uses a second susceptor having a mounting surface with a second curvature different from the first curvature. The transfer process transfers the substrate from the first susceptor to the second susceptor between the first and second growth processes.
摘要翻译： 一种制造半导体发光器件的方法包括在衬底上顺序地生长第一导电类型半导体层，有源层和第二导电类型半导体层，以形成发光层。 发光层的形成包括第一生长过程，第二生长过程和转移过程。 第一生长过程使用具有第一曲率的安装表面的第一感受器。 第二生长过程使用具有不同于第一曲率的第二曲率的安装表面的第二感受器。 转移过程在第一和第二生长过程之间将衬底从第一感受器转移到第二感受器。
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公开(公告)号：US20130146842A1
公开(公告)日：2013-06-13
申请号：US13712656
申请日：2012-12-12
发明人： Nam Sung KIM , Dong Ik Shin , Hyun Wook Shim , Dong Joon Kim , Young Sun Kim , Jung Seung YANG
IPC分类号： H01L33/06
摘要： A semiconductor light emitting device includes first conductivity type and second conductivity type semiconductor layers, an active layer disposed between the semiconductor layers and having a structure in which one or more quantum well layers and one or more quantum barrier layers are alternately disposed An electron blocking layer is disposed between the active layer and the second conductivity type semiconductor layer. A capping layer is disposed between the active layer and the electron blocking layer and blocking a dopant element from being injected into the active layer from the second conductivity type semiconductor layer.
摘要翻译： 半导体发光器件包括第一导电类型和第二导电类型半导体层，有源层设置在半导体层之间并且具有其中一个或多个量子阱层和一个或多个量子势垒层交替布置的结构。电子阻挡层 设置在有源层和第二导电类型半导体层之间。 覆盖层设置在有源层和电子阻挡层之间，并阻止掺杂剂元素从第二导电类型半导体层注入到有源层中。
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3.发明公开公开(公告)号：US20240086345A1
公开(公告)日：2024-03-14
申请号：US18511725
申请日：2023-11-16
发明人： Sang-Hyuk KWON , Nam Sung KIM , Kyomin SOHN , Jaeyoun YOUN
IPC分类号： G06F13/16 , H01L25/065
CPC分类号： G06F13/1668 , H01L25/0657 , G11C8/10
摘要： A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
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公开(公告)号：US20210150319A1
公开(公告)日：2021-05-20
申请号：US16892637
申请日：2020-06-04
发明人： Hak-Soo YU , Nam Sung KIM , Kyomin SOHN , Jaeyoun YOUN
IPC分类号： G06N3/063 , G11C11/54 , G11C11/4096 , G11C11/408 , G11C11/56 , G11C11/4091 , G06N3/08
摘要： A neuromorphic device includes a memory cell array that includes first memory cells corresponding to a first address and storing first weights and second memory cells corresponding to a second address and storing second weights, and a neuron circuit that includes an integrator summing first read signals from the first memory cells and an activation circuit outputting a first activation signal based on a first sum signal of the first read signals output from the integrator.
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公开(公告)号：US20150240358A1
公开(公告)日：2015-08-27
申请号：US14506182
申请日：2014-10-03
发明人： Nam Sung KIM , Jong Won JANG , Sung Min CHOI , Sang Heon HAN , Suk Ho YOON , Jeong Wook LEE
IPC分类号： C23C16/458 , C23C16/46
CPC分类号： C23C16/4586 , C23C16/45508 , C23C16/4584
摘要： There is provided a susceptor. The susceptor includes: a body having a first surface, a second surface opposite the first surface, and an outer side surface connecting the first surface and the second surface; at least one pocket recessed from the first surface to accommodate at least one wafer therein, respectively; at least one tunnel respectively located below the pocket and extending from a center of the body to the outer side surface; at least one connecting channel each of which connects each of the pocket to each of the tunnel; and a supply line connected to the tunnel at the center of the body and supplying a gas from an outside in order for the gas to flow from the center of the body to the outer side surface.
摘要翻译： 提供了一个感受器。 感受体包括：主体，其具有第一表面，与第一表面相对的第二表面和连接第一表面和第二表面的外侧表面; 分别从所述第一表面凹入以容纳至少一个晶片的至少一个凹坑; 至少一个隧道分别位于所述口袋下方并从所述主体的中心延伸到所述外侧表面; 至少一个连接通道，每个连接通道将每个口袋连接到每个隧道; 以及在主体的中心连接到隧道的供应管线，并且从外部供应气体以使气体从主体的中心流向外侧表面。
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公开(公告)号：US20210157751A1
公开(公告)日：2021-05-27
申请号：US16934497
申请日：2020-07-21
发明人： Sang-Hyuk KWON , Nam Sung KIM , Kyomin SOHN , Jaeyoun YOUN
IPC分类号： G06F13/16 , H01L25/065
摘要： A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.
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公开(公告)号：US20130228792A1
公开(公告)日：2013-09-05
申请号：US13784916
申请日：2013-03-05
发明人： Hyun Wook SHIM , Tonk Ik SHIN , Nam Sung KIM , Young Sun KIM
IPC分类号： H01L33/12
CPC分类号： H01L33/12 , H01L33/02 , H01L33/641 , H01L33/642 , H01L2224/48091 , H01L2224/49107 , H01L2224/73265 , H01L2924/00014
摘要： A semiconductor light emitting device includes a substrate having a through hole formed in a thickness direction thereof and a conductive nanowire provided in at least a portion of the through hole, and a light emitting structure formed on the substrate and including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer.
摘要翻译： 一种半导体发光器件包括：具有沿其厚度方向形成的通孔的基板和设置在所述通孔的至少一部分中的导电纳米线;以及形成在所述基板上并包括第一导电半导体层的发光结构， 有源层和第二导电半导体层。
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8.发明申请公开(公告)号：US20190354292A1
公开(公告)日：2019-11-21
申请号：US16524749
申请日：2019-07-29
发明人： Seong-Il O , Nam Sung KIM , Young-Hoon SON , Chan-Kyung KIM , Ho-Young SONG , Jung Ho AHN , Sang-Joon HWANG
摘要： A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.
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