公开(公告)号：US09697111B2

公开(公告)日：2017-07-04

申请号：US13957968

申请日：2013-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hee Yoo ,  Sung Hyun Lee ,  Dong Soo Kang

IPC: G11C7/10 ,  G06F12/02 ,  G06F12/0864 ,  G06F12/0897 ,  G11C11/408

CPC classification number: G06F12/02 ,  G06F12/023 ,  G06F12/0864 ,  G06F12/0897 ,  G06F2212/205 ,  G06F2212/304 ,  G11C7/1072 ,  G11C11/408

Abstract: A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part.

公开(公告)号：US09747998B2

公开(公告)日：2017-08-29

申请号：US14462843

申请日：2014-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sua Kim ,  Dongsoo Kang ,  Chulwoo Park ,  Jun Hee Yoo ,  Hak-Soo Yu ,  Jaeyoun Youn ,  Sung Hyun Lee ,  Jinsu Jung ,  Hyojin Choi

IPC: G11C17/16 ,  G11C29/02 ,  G11C29/42 ,  G11C29/44 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/42 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/4402

Abstract: A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area.

公开(公告)号：US09606916B2

公开(公告)日：2017-03-28

申请号：US14307994

申请日：2014-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Hyun Lee ,  Jun Hee Yoo ,  Dongsoo Kang ,  Il Park ,  Kiyeon Lee ,  Euicheol Lim

IPC: G06F12/06

CPC classification number: G06F12/0607 ,  Y02D10/13

Abstract: A memory system includes a high-bandwidth memory device, the high-bandwidth memory device having a relatively high operation bandwidth, the high-bandwidth memory device having a plurality of access channels. A low-bandwidth memory device has a relatively low operation bandwidth relative to the high-bandwidth memory device, the low-bandwidth memory device having one or more access channels. An interleaving unit performs a memory interleave operation among the plurality of access channels of the high-bandwidth memory device and an access channel of the one or more access channels of the low-bandwidth memory device.

公开(公告)号：US09348679B2

公开(公告)日：2016-05-24

申请号：US14465105

申请日：2014-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Hee Yoo ,  Sung Hyun Lee ,  Dongsoo Kang ,  Sua Kim ,  Haksoo Yu ,  Jaeyoun Youn ,  Hyojin Choi

IPC: G06F11/10 ,  G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/44

CPC classification number: G06F11/00 ,  G11C8/06 ,  G11C11/401 ,  G11C29/78 ,  G11C2029/4402

Abstract: A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

Abstract translation: 提供了不良页面管理系统以保证诸如DRAM之类的易失性半导体存储器件的产量。 DRAM中存在不良页面列表。 存储器控制器中的页面重新映射器与调度单元的正常操作并行执行页面重映射操作，以执行延迟开销隐藏功能。 DRAM的芯片尺寸减小或最小化。 DRAM控制器执行延迟开销隐藏功能来控制DRAM。