公开(公告)号：US11195997B2

公开(公告)日：2021-12-07

申请号：US16826778

申请日：2020-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhwan Paik ,  Yongjin Park ,  Jinwook Yang ,  Gyuhwan Oh ,  Jiyoon Chung

IPC: H01L47/00 ,  H01L45/00 ,  H01L23/528 ,  H01L27/24

Abstract: A variable resistance memory device includes a first conductive line structure having an adiabatic line therein on a substrate, a variable resistance pattern contacting an upper surface of the first conductive line structure, a low resistance pattern contacting an upper surface of the variable resistance pattern, a selection structure on the low resistance pattern, and a second conductive line on the selection structure.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.

公开(公告)号：US11502132B2

公开(公告)日：2022-11-15

申请号：US17158287

申请日：2021-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwook Yang ,  Gyuhwan Oh ,  Junhwan Paik ,  Jiyoon Chung

IPC: H01L27/24 ,  H01L45/00

Abstract: A semiconductor memory device including a substrate; a first conductive line on the substrate and extending in a first direction that is parallel to an upper surface of the substrate; a second conductive line extending in a second direction that intersects the first direction; a memory cell between the conductive lines and including a lower electrode pattern, a data storage element, an intermediate electrode pattern, a switching element, and an upper electrode pattern sequentially stacked on the first conductive line; and a sidewall spacer on a side surface of the memory cell, wherein the side surface of the memory cell includes a first concave portion at a side surface of the switching element, and the sidewall spacer includes a first portion on a side surface of the upper electrode pattern, and a second portion on the first concave portion, the second portion being thicker than the first portion.

公开(公告)号：US20240096956A1

公开(公告)日：2024-03-21

申请号：US18370663

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjoo Na ,  Woobin Song ,  Jinwook Yang ,  Cheoljin Yun ,  Dongkyu Lee ,  Yoshinao Harada

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/66553

Abstract: An integrated circuit semiconductor device includes a nanosheet extending above a substrate in a first horizontal direction, a gate electrode extending in a second horizontal direction while surrounding the nanosheet with a gate insulating layer therebetween, a first source/drain region on a side of the nanosheet, and a second source/drain region on another side of the nanosheet, wherein the first source/drain region includes first silicide layers provided inward from surfaces of the nanosheet, first metal layers surrounding the nanosheet from upper and lower sides of the first silicide layers, and a first nanosheet region provided between the first silicide layers, wherein the second source/drain region includes second silicide layers formed inward from the surfaces of the nanosheet, second metal layers surrounding the nanosheet from upper and lower sides of the second silicide layers, and a second nanosheet region provided between the second silicide layers.