公开(公告)号：US20240096956A1

公开(公告)日：2024-03-21

申请号：US18370663

申请日：2023-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjoo Na ,  Woobin Song ,  Jinwook Yang ,  Cheoljin Yun ,  Dongkyu Lee ,  Yoshinao Harada

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4933 ,  H01L29/66553

Abstract: An integrated circuit semiconductor device includes a nanosheet extending above a substrate in a first horizontal direction, a gate electrode extending in a second horizontal direction while surrounding the nanosheet with a gate insulating layer therebetween, a first source/drain region on a side of the nanosheet, and a second source/drain region on another side of the nanosheet, wherein the first source/drain region includes first silicide layers provided inward from surfaces of the nanosheet, first metal layers surrounding the nanosheet from upper and lower sides of the first silicide layers, and a first nanosheet region provided between the first silicide layers, wherein the second source/drain region includes second silicide layers formed inward from the surfaces of the nanosheet, second metal layers surrounding the nanosheet from upper and lower sides of the second silicide layers, and a second nanosheet region provided between the second silicide layers.

公开(公告)号：US12166097B2

公开(公告)日：2024-12-10

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20240282864A1

公开(公告)日：2024-08-22

申请号：US18432351

申请日：2024-02-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongkyu Lee ,  Sungil Park ,  Jaehyun Park ,  Jinwook Yang ,  Jinchan Yun ,  Cheoljin Yun ,  Daewon Ha ,  Kyuman Hwang

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/78696 ,  H01L21/823807 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: An integrated circuit semiconductor device with three dimensional transistors includes two gate-all-around transistors or multi-bridge channel field effect transistors may be vertically stacked to reduce unit area. The two stacked transistors may be separated by an isolation insulating layer. The two stacked transistors may be positioned on two opposite sides of the isolation insulating layer, with the structure of the two stacked transistors positioned in an opposite manner. According to embodiments of the present disclosure, metal wiring layers may be connected to the two stacked transistors at their far ends, away from the isolation insulating layer. A method for manufacturing an integrated circuit semiconductor device according to the present disclosure is described. Accordingly, aspects described herein may result in reduced unit area and easy manufacture of metal wiring layer connected to the transistors.

公开(公告)号：US11888044B2

公开(公告)日：2024-01-30

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil Park ,  Jae Hyun Park ,  Kyungho Kim ,  Cheoljin Yun ,  Daewon Ha

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/165 ,  H01L21/82

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.