公开(公告)号：US20160380075A1

公开(公告)日：2016-12-29

申请号：US15170230

申请日：2016-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Yup CHUNG ,  Hyun-Jo KIM ,  Seong-Yul PARK ,  Se-Wan PARK ,  Jong-Mil YOUN ,  Jeong-Hyo LEE ,  Hwa-Sung RHEE ,  Hee-Don JEONG ,  Ji-Yong HA

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L27/092 ,  H01L29/161

CPC classification number: H01L29/66545 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7854 ,  H01L29/7855

Abstract: A semiconductor device includes a fin-type pattern including a first short side and a second short side opposed to each other, a first trench in contact with the first short side, a second trench in contact with the second short side, a first field insulating film in the first trench, the first field insulating film including a first portion and a second portion arranged sequentially from the first short side, and a height of the first portion being different from a height of the second portion, a second field insulating film in the second trench, and a first dummy gate on the first portion of the first field insulating film.

Abstract translation: 半导体器件包括鳍状图案，其包括彼此相对的第一短边和第二短边，与第一短边接触的第一沟槽，与第二短边接触的第二沟槽，第一场绝缘 所述第一场绝缘膜包括从所述第一短边顺序布置的第一部分和第二部分，并且所述第一部分的高度不同于所述第二部分的高度;第二场绝缘膜， 第二沟槽和第一场绝缘膜的第一部分上的第一伪栅极。

公开(公告)号：US20150364574A1

公开(公告)日：2015-12-17

申请号：US14579627

申请日：2014-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Youn KIM ,  Dong-Hyun ROH ,  Sang-Duk PARK ,  Il-Young YOON ,  Jeong-Nam HAN ,  Jong-Mil YOUN

IPC: H01L29/66 ,  H01L21/3105 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L27/088 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66545 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/66636

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure including a dummy gate insulation layer pattern, a dummy gate electrode and a gate mask sequentially stacked are formed on a substrate. An interlayer insulating layer including tonen silazane (TOSZ) is formed on the substrate to cover the dummy gate structure. An upper portion of the interlayer insulating layer is planarized until a top surface of the gate mask is exposed to form an interlayer insulating layer pattern. The exposed gate mask, and the dummy gate electrode and the dummy gate insulation layer pattern under the gate mask are removed to form an opening exposing a top surface of the substrate. The dummy gate insulation layer pattern is removed using an etchant including hydrogen fluoride (HF), but the interlayer insulating layer pattern remains. A gate structure is formed to fill the opening.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成包括虚拟栅极绝缘层图案，虚拟栅极电极和栅极掩模的虚拟栅极结构。 在基板上形成包含蒙片硅氮烷（TOSZ）的层间绝缘层，以覆盖虚拟栅极结构。 层间绝缘层的上部被平坦化，直到露出栅极掩模的顶表面以形成层间绝缘层图案。 除去栅极掩模下的露出的栅极掩模，伪栅极电极和伪栅极绝缘层图案，以形成露出衬底顶表面的开口。 使用包括氟化氢（HF）的蚀刻剂去除伪栅极绝缘层图案，但是残留层间绝缘层图案。 形成浇口结构以填充开口。

公开(公告)号：US20140167177A1

公开(公告)日：2014-06-19

申请号：US14081543

申请日：2013-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hun KIM ,  Ju-Youn KIM ,  Koung-Min RYU ,  Jong-Mil YOUN ,  Jong-Ho LEE

IPC: H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1029

Abstract: A semiconductor device includes a channel layer over an active region, first and second field regions adjacent the active region, and a gate structure over the channel layer and portions of the first and second field regions. The first and second field regions include grooves adjacent respective sidewalls of the channel layer, and bottom surfaces of the grooves are below a bottom surface of the channel layer.

Abstract translation: 半导体器件包括在有源区上的沟道层，与有源区相邻的第一和第二场区以及沟道层上的栅极结构以及第一和第二场区的部分。 第一和第二场区域包括与沟道层的相应侧壁相邻的沟槽，并且沟槽的底表面在沟道层的底表面下方。