公开(公告)号：US20240079284A1

公开(公告)日：2024-03-07

申请号：US18140417

申请日：2023-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Woo MYUNG ,  Gun LEE

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3128 ,  H01L21/565 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06541 ,  H01L2225/1058

Abstract: A semiconductor package including a first redistribution structure including a first redistribution layer disposed therein, a first semiconductor chip disposed on the first redistribution structure, an insulating layer surrounding a sidewall of the first semiconductor chip, the insulating layer spaced apart from the first semiconductor chip in a horizontal direction, a first connection structure extending through the insulating layer in a vertical direction, connected to the first redistribution structure, and includes a first via disposed inside the insulating layer. A second connection structure disposed between the first semiconductor chip and the first connection structure, extends through the insulating layer in the vertical direction, connected to the first redistribution structure, and includes a second via disposed inside the insulating layer. A molding layer covering the first semiconductor chip, a sidewall and an upper surface of the insulating layer. At least a portion of the molding layer disposed between the first and second vias.

公开(公告)号：US20240047327A1

公开(公告)日：2024-02-08

申请号：US18309070

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gun LEE ,  Jun Woo MYUNG

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/3107 ,  H01L24/20 ,  H01L2224/221 ,  H01L2224/19 ,  H01L24/19

Abstract: Provided is a semiconductor package. The semiconductor package may include a first redistribution structure, a first semiconductor chip including a first surface and a second surface, the first surface being disposed to face the first redistribution structure, a second redistribution structure disposed on the second surface of the first semiconductor chip and including a second insulating layer and a second redistribution layer, a first sealing layer disposed between the first and second redistribution structures and configured to cover the second surface of the first semiconductor chip, and a connection structure configured to connect the first and the second redistribution structures, wherein the second redistribution layer includes a first via and a second via on the first via, wherein the first via includes first and second seed layers, and a conductive layer on the second seed layer, and wherein the first sealing layer includes a photosensitive insulating material.

公开(公告)号：US20200083163A1

公开(公告)日：2020-03-12

申请号：US16684907

申请日：2019-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Akihisa KUROYANAGI ,  Jun Woo MYUNG ,  Eun Sil KIM ,  Yeong A KIM

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/538

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.

公开(公告)号：US20250079393A1

公开(公告)日：2025-03-06

申请号：US18748354

申请日：2024-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Cheon PARK ,  Un-Byoung KANG ,  Ku Young KIM ,  Jun Woo MYUNG ,  Seung-Jin LEE ,  Ji-Seok HONG

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes: a first semiconductor chip including a first substrate and a first through electrode passing through the first substrate, wherein the first substrate has a first active surface and a first non-active surface; a chip structure including a plurality of second semiconductor chips stacked on the first semiconductor chip, wherein each second semiconductor chip includes a second substrate and a second through electrode passing through the second substrate; and a third semiconductor chip disposed on the chip structure, and including a third substrate, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width.

公开(公告)号：US20200152538A1

公开(公告)日：2020-05-14

申请号：US16746181

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Woo MYUNG ,  Akihisa KUROYANAGI ,  Yeong A. KIM ,  Eun Sil KIM

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/10 ,  H01L23/29

Abstract: A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

公开(公告)号：US20190371692A1

公开(公告)日：2019-12-05

申请号：US16178224

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Akihisa KUROYANAGI ,  Jun Woo MYUNG ,  Jae Kul LEE

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: An electronic component package includes a core member including an insulating layer, and having a first through-hole passing through the insulating layer, a semiconductor chip disposed in the first through-hole, and having an active surface on which a connection pad is disposed, and an inactive surface opposing the active surface, an encapsulant encapsulating the core member and the semiconductor chip, and filling at least a portion of the first through-hole, a connection member disposed on the core member and the semiconductor chip, and including a redistribution layer electrically connected to the connection pad, a backside metal layer disposed on the encapsulant, and covering at least the inactive surface of the semiconductor chip, and a backside metal via passing through the encapsulant, and connecting the backside metal layer to one side of the insulating layer. The backside metal via is in contact with the one side of the insulating layer.