公开(公告)号：US11182518B2

公开(公告)日：2021-11-23

申请号：US16127692

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Yub Ie ,  Jung Geun Jee ,  Sung Youn Chung ,  Jae Myung Choe

IPC: G06F30/20 ,  C23C16/455 ,  G06F30/17

Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.

公开(公告)号：US11094709B2

公开(公告)日：2021-08-17

申请号：US16441657

申请日：2019-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Jung Geun Jee

IPC: H01L29/792 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11568

Abstract: A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer.

公开(公告)号：US20190228120A1

公开(公告)日：2019-07-25

申请号：US16127692

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Yub Ie ,  Jung Geun Jee ,  Sung Youn Chung ,  Jae Myung Choe

IPC: G06F17/50 ,  C23C16/455

Abstract: An apparatus for generating 3D shape data of a showerhead includes: a data processor that generates data sets comprising information indicating values of a first distance between an upper surface of a wafer and a showerhead, information indicating positions on the wafer and information about a fluid flow physical quantity value and determines a function representing a relationship among the various information; an input unit that receives condition data comprising a target fluid flow physical quantity value for each of the positions; and a database that stores information about the function. The data processor obtains information about a second distance, which has the target fluid flow physical quantity value, between the upper surface of the wafer and the showerhead at each of the positions, extracts spatial coordinate information of a lower surface of the showerhead, and generates 3D shape data of the showerhead using the spatial coordinate information.

公开(公告)号：US11864383B2

公开(公告)日：2024-01-02

申请号：US17495614

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Jung Geun Jee

IPC: H10B41/30 ,  H10B43/27 ,  H01L29/10 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H10B43/27 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76832 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/40117

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

公开(公告)号：US11164884B2

公开(公告)日：2021-11-02

申请号：US16359009

申请日：2019-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Jung Geun Jee

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

公开(公告)号：US09905664B2

公开(公告)日：2018-02-27

申请号：US15604646

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.