公开(公告)号：US09978932B2

公开(公告)日：2018-05-22

申请号：US15057101

申请日：2016-02-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjoon Kwon ,  Sechung Oh ,  Vladimir Urazaev ,  Ken Tokashiki ,  Jongchul Park ,  Gwang-Hyun Baek ,  Jaehun Seo ,  Sangmin Lee

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16 ,  H01L45/00 ,  H01L27/24 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

公开(公告)号：US09577183B2

公开(公告)日：2017-02-21

申请号：US14611717

申请日：2015-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung-Sun Kim ,  Woo-Jin Kim ,  Ken Tokashiki

IPC: H01L43/12 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L27/228

Abstract: In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed.

Abstract translation: 在制造MRAM器件的方法中，在基片上形成下电极。 第一磁性层，隧道势垒层和第二磁性层依次形成在下部电极层上。 在第二磁性层上形成蚀刻掩模。 执行其中第一离子束和第二离子束同时发射到衬底上的离子束蚀刻工艺，以形成包括第一磁性层图案，隧道层图案和第二磁性层图案的MTJ结构 磁性层，隧道势垒层和第二磁性层，在执行离子束蚀刻处理之后，MTJ结构没有剩余副产物。

公开(公告)号：US09496488B2

公开(公告)日：2016-11-15

申请号：US14070471

申请日：2013-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjoon Kwon ,  Sechung Oh ,  Vladimir Urazaev ,  Ken Tokashiki ,  Jongchul Park ,  Gwang-Hyun Baek ,  Jaehun Seo ,  Sangmin Lee

IPC: H01L43/08 ,  H01L27/22 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/02 ,  H01L43/10 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

Abstract: Provided are semiconductor devices and methods of fabricating the same. The semiconductor device may include lower wires, upper wires crossing the lower wires, select elements provided at intersections between the lower and upper wires, and memory elements provided between the select elements and the upper wires. Each of the memory elements may include a lower electrode having a top width greater than a bottom width, and a data storage layer including a plurality of magnetic layers stacked on a top surface of the lower electrode and having a rounded edge.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件可以包括下部布线，穿过下部布线的上部布线，在下部布线和上部布线之间的交叉处提供的选择元件以及设置在选择元件和上部布线之间的存储元件。 每个存储元件可以包括具有大于底部宽度的顶部宽度的下部电极，以及包括堆叠在下部电极的顶表面上并且具有圆形边缘的多个磁性层的数据存储层。