-
公开(公告)号:US10650910B2
公开(公告)日:2020-05-12
申请号:US16249543
申请日:2019-01-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Changwook Jeong , Sanghoon Myung , Min-Chul Park , Jeonghoon Ko , Jisu Ryu , Hyunjae Jang , Hyungtae Kim , Yunrong Li , Min Chul Jeon
Abstract: A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.
-
公开(公告)号:US20250104217A1
公开(公告)日:2025-03-27
申请号:US18784343
申请日:2024-07-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Bo Gyeong Kang , Ye Ji Kim , Min-Chul Park , Byoung Seon Choi , Seong Ryeol Kim , Young-Gu Kim , Jae Myung Choe
IPC: G06T7/00 , G06V10/44 , G06V10/75 , G06V10/762
Abstract: A computing device of predicting potential predicting potential defect-inducing factors within a semiconductor layout is provided. The computing device comprising: a machine learning module, calculating predicted measurement data corresponding to at least one first semiconductor layout image among a plurality of semiconductor layout mages after being trained based on the plurality of semiconductor layout images and corresponding real measurement data and an image explanation module generating an attribution map image of the predicted measurement data based on an image regression model utilizing an integrated gradient (IG) manner, analyzing the attribution map image and detecting elements within the attribution map image with attribution values with high sensitivity to the predicted measurement data as potential defect-inducing factors in advance.
-
公开(公告)号:US11741596B2
公开(公告)日:2023-08-29
申请号:US16599733
申请日:2019-10-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Min-Chul Park , Ami Ma , Jisu Ryu , Changwook Jeong
IPC: G06K9/00 , G06T7/00 , H01L21/67 , G01N21/956 , G01N21/95 , G06T5/00 , G01N21/88 , G06V10/70 , G06V10/82 , G06V10/74
CPC classification number: G06T7/001 , G01N21/8851 , G01N21/9501 , G01N21/95607 , G06T5/002 , G06T7/0004 , G06V10/70 , G06V10/74 , G06V10/82 , H01L21/67288 , G01N2021/8854 , G01N2021/8867 , G01N2021/95615 , G06T2207/20081 , G06T2207/30141 , G06T2207/30148
Abstract: A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.
-
公开(公告)号:US11886783B2
公开(公告)日:2024-01-30
申请号:US18153573
申请日:2023-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sanghoon Myung , Hyunjae Jang , In Huh , Hyeon Kyun Noh , Min-Chul Park , Changwook Jeong
IPC: G06F30/27 , G06N3/08 , G06N3/10 , G06F30/398 , G06N3/044
CPC classification number: G06F30/27 , G06F30/398 , G06N3/044 , G06N3/08 , G06N3/10
Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.
-
公开(公告)号:US20230142367A1
公开(公告)日:2023-05-11
申请号:US18153573
申请日:2023-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sanghoon MYUNG , Hyunjae Jang , In Huh , Hyeon Kyun Noh , Min-Chul Park , Changwook Jeong
IPC: G06F30/27 , G06N3/08 , G06N3/10 , G06F30/398 , G06N3/044
CPC classification number: G06F30/27 , G06N3/08 , G06N3/10 , G06F30/398 , G06N3/044
Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.
-
公开(公告)号:US11574095B2
公开(公告)日:2023-02-07
申请号:US16906038
申请日:2020-06-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sanghoon Myung , Hyunjae Jang , In Huh , Hyeon Kyun Noh , Min-Chul Park , Changwook Jeong
IPC: G06F30/27 , G06N3/08 , G06N3/10 , G06N3/04 , G06F30/398
Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.
-
7.
公开(公告)号:US10055829B2
公开(公告)日:2018-08-21
申请号:US15252613
申请日:2016-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Chul Park , Je-Hyun Lee , Jeong-Hoon Ko , Young-Gu Kim , Keun-Ho Lee
CPC classification number: G06T7/0004 , G06T5/002 , G06T7/12 , G06T7/62 , G06T2207/10061 , G06T2207/20024 , G06T2207/20048 , G06T2207/20216 , G06T2207/30148
Abstract: A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.
-
8.
公开(公告)号:US20170109896A1
公开(公告)日:2017-04-20
申请号:US15252613
申请日:2016-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Min-Chul Park , Je-Hyun Lee , Jeong-Hoon Ko , Young-Gu Kim , Keun-Ho Lee
CPC classification number: G06T7/0004 , G06T5/002 , G06T7/12 , G06T7/62 , G06T2207/10061 , G06T2207/20024 , G06T2207/20048 , G06T2207/20216 , G06T2207/30148
Abstract: A thickness of a first layer in a structure may be measured based on an original image of the structure. A first boundary of the first layer may be identified in the original image. A second boundary that is substantially indistinguishable in the original image may be identified based on converting the original image into a first image based on the first boundary and generating a second image based on filtering the first image. The first image may be generated based on adjusting partial image portions of the original image to align the representation of the first boundary with an axis line, such that the first image includes a representation of the first boundary that extends substantially in parallel with the axis line. The second boundary may be identified from the second image, and the thickness of the layer may be determined based on the identified first and second boundaries.
-
-
-
-
-
-
-