公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20150162332A1

公开(公告)日：2015-06-11

申请号：US14543140

申请日：2014-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Bon-Young KOO ,  Seok-Hoon KIM ,  Chul KIM ,  Kwan-Heum LEE ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/161

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/785

Abstract: An integrated circuit device includes an electrically conductive pattern on a substrate. This electrically conductive pattern may be a gate pattern of a field effect transistor. A first electrically insulating spacer is provided on a sidewall of the electrically conductive pattern. The first electrically insulating spacer includes a first lower spacer and a first upper spacer, which extends on the first lower spacer and has a side surface vertically aligned with a corresponding side surface of the first lower spacer. The first upper spacer has a greater dielectric constant relative to a dielectric constant of the first lower spacer. A pair of parallel channel regions may also be provided, which protrude from a surface of the substrate. The electrically conductive pattern may surround top and side surfaces of the pair of parallel channel regions.

Abstract translation: 集成电路器件包括在衬底上的导电图案。 该导电图案可以是场效应晶体管的栅极图案。 第一电绝缘垫片设置在导电图案的侧壁上。 第一电绝缘间隔件包括第一下间隔件和第一上间隔件，其在第一下间隔件上延伸并且具有与第一下间隔件的对应侧表面垂直对准的侧表面。 第一上间隔物相对于第一下间隔物的介电常数具有更大的介电常数。 还可以设置一对平行的通道区域，其从衬底的表面突出。 导电图案可以围绕该对平行通道区域的顶表面和侧表面。

公开(公告)号：US20140374827A1

公开(公告)日：2014-12-25

申请号：US14259212

申请日：2014-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Chan SUH ,  Chung-Geun KOH ,  Seong-Hoon JEONG ,  Kwan-Heum LEE ,  Hwa-Sung RHEE ,  Gyeom KIM

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L29/66545

Abstract: A semiconductor device includes a fin type active pattern protruding above a device isolation layer, a gate electrode on the device isolation layer and intersecting the fin type active pattern, an elevated source/drain on the fin type active pattern at both sides of the gate electrode, and a fin spacer on a side wall of the fin type active pattern, the fin spacer having a low dielectric constant and being between the device isolation layer and the elevated source/drain.

Abstract translation: 半导体器件包括突出在器件隔离层上方的翅片型有源图案，器件隔离层上的栅电极并与鳍式有源图案相交，栅极电极两侧的翅片型有源图案上的升高的源极/漏极 以及在翅片型有源图案的侧壁上的翅片间隔件，翅片间隔件具有低介电常数并且位于器件隔离层和升高的源极/漏极之间。