公开(公告)号：US20170148797A1

公开(公告)日：2017-05-25

申请号：US15351739

申请日：2016-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L29/45 ,  H01L29/161 ,  H01L23/528 ,  H01L27/088 ,  H01L29/08

CPC classification number: H01L27/1104 ,  H01L21/823431 ,  H01L23/485 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20160240441A1

公开(公告)日：2016-08-18

申请号：US15136450

申请日：2016-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung-Gil KANG ,  Sung-Bong KIM ,  Chang-Woo OH ,  Dong-Won KIM

IPC: H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。

公开(公告)号：US20220415905A1

公开(公告)日：2022-12-29

申请号：US17929513

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Bum KIM ,  Myung-Gil KANG ,  Kang-Hun MOON ,  Cho-Eun LEE ,  Su-Jin JUNG ,  Min-Hee CHOI ,  Yang XU ,  Dong-Suk SHIN ,  Kwan-Heum LEE ,  Hoi-Sung CHUNG

IPC: H01L27/11 ,  H01L23/528 ,  H01L29/66 ,  H01L27/088 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L23/485 ,  H01L27/092 ,  H01L29/165

Abstract: A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer structure. The first active fin may be on a first region of a substrate. The second active fins may be on a second region of the substrate. The first and second gate structures may be on the first and second active fins, respectively. The first source/drain layer structure may be on a portion of the first active fin that is adjacent to the first gate structure. The second source/drain layer structure may commonly contact upper surfaces of the second active fins adjacent to the second gate structure. A top surface of the second source/drain layer structure may be further from the surface of the substrate than a top surface of the first source/drain layer structure is to the surface of the substrate.

公开(公告)号：US20160049968A1

公开(公告)日：2016-02-18

申请号：US14825017

申请日：2015-08-12

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Myung-Gil KANG ,  Wan CHOI ,  Dae-Kyu SHIN ,  Sang-Wook SUH

IPC: H04B1/04

CPC classification number: H04B1/126

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-Generation (4G) communication system such as a Long Term Evolution (LTE). A method for controlling interference in a signal transmitting apparatus in a mobile communication system is provided. The method includes transmitting data to a first signal receiving apparatus using a plurality of channels; receiving information indicating whether at least one of the plurality of channels exists as an interference channel in a second signal receiving apparatus from the second signal receiving apparatus; receiving interference control information for controlling interference for the second signal receiving apparatus from the second signal receiving apparatus based on the received information, and generating interference control data based on the interference control information; and transmitting the interference control data to the first signal receiving apparatus.

Abstract translation: 本公开涉及提供用于支持超过第四代（4G）通信系统（例如长期演进（LTE））的更高数据速率的第5代（5G）或5G通信系统。 提供了一种用于控制移动通信系统中的信号发送装置中的干扰的方法。 该方法包括使用多个信道向第一信号接收设备发送数据; 从所述第二信号接收装置接收指示所述多个信道中的至少一个信道是否存在于第二信号接收装置中的干扰信道的信息; 基于接收到的信息，从第二信号接收装置接收用于控制第二信号接收装置的干扰的干扰控制信息，根据干扰控制信息生成干扰控制数据; 以及将所述干扰控制数据发送到所述第一信号接收装置。

公开(公告)号：US20140239255A1

公开(公告)日：2014-08-28

申请号：US14162052

申请日：2014-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung-Gil KANG ,  Sung-Bong KIM ,  Chang-Woo OH ,  Dong-Won KIM

IPC: H01L29/775 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Abstract translation: 集成电路器件包括第一晶体管，其具有在第一源极/漏极之间的第一沟道和在第二源极/漏极之间具有第二沟道的第二晶体管。 第一晶体管基于第一电流量而工作，并且第二晶体管基于不同于第一电流量的第二电流量来操作。 第一和第二通道具有固定的通道宽度。 固定通道宽度可以基于包括在第一和第二晶体管中的翅片或纳米线。