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    Variable resistance memory device
    1.
    发明授权
    Variable resistance memory device 有权

    公开(公告)号：US10923654B2

    公开(公告)日：2021-02-16

    申请号：US16426216

    申请日：2019-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ilmok Park ,  Kyusul Park ,  Seulji Song ,  Kwang-Woo Lee

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: A variable resistance memory device includes a word line extending in a first direction, a bit line on the word line and extending in a second direction intersecting the first direction, a switching pattern between the bit line and the word line, a phase change pattern between the switching pattern and the word line, and a bottom electrode between the phase change pattern and the word line, wherein the phase change pattern has a bottom area greater than a top area of the bottom electrode, a thickness of the phase change pattern being greater than a thickness of the bottom electrode, and wherein the bottom and top areas are defined in the first and second directions, and the thicknesses are defined in a third direction intersecting the first and second directions.

    Methods of manufacturing a semiconductor device
    3.
    发明授权
    Methods of manufacturing a semiconductor device 有权

    公开(公告)号：US10049943B2

    公开(公告)日：2018-08-14

    申请号：US15171120

    申请日：2016-06-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jae-Hyun Yeo ,  Jae-Suk Kwon ,  Kwang-Woo Lee ,  Eun-Seong Lee

    IPC: H01L21/8238 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

    Abstract: A method of manufacturing a semiconductor device includes forming a first gate structure on a substrate, the first gate structure including a gate insulation layer, a gate electrode, and a hard mask sequentially stacked on the substrate, forming a preliminary spacer layer on sidewalls of the first gate structure and the substrate, the preliminary spacer layer including silicon nitride, implanting molecular ions into the preliminary spacer layer to form a spacer layer having a dielectric constant lower than a dielectric constant of the preliminary spacer layer, anisotropically etching the spacer layer to form spacers on the sidewalls of the first gate structure, and forming impurity regions at upper portions of the substrate adjacent to the first gate structure.

    Method of refreshing volatile memory device
    4.
    发明授权
    Method of refreshing volatile memory device 有权
    刷新易失性存储器件的方法

    公开(公告)号：US09129702B2

    公开(公告)日：2015-09-08

    申请号：US14336337

    申请日：2014-07-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dae-Jeong Kim ,  Heon Lee ,  Hoon-Chang Yang ,  Kwang-Woo Lee

    IPC: G11C7/00 ,  G11C11/406 ,  G11C29/02

    CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/02 ,  G11C2211/4065 ,  G11C2211/4068

    Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

    Abstract translation: 提供了一种刷新易失性存储器的方法。 该方法包括根据短于刷新周期的弱小区刷新周期来存储关于要更新的​​弱小区行地址的地址信息，执行用于生成刷新行地址的计数操作，将刷新行地址与 地址信息，当比较结果表明地址信息的刷新行地址和弱单元行地址彼此一致时刷新弱单元行地址，通过改变地址信息的指针来改变弱单元行地址 ，并且根据弱小区刷新周期刷新改变的弱小区行地址。

    Nonvolatile Memory Device and Writing Method Thereof
    5.
    发明申请
    Nonvolatile Memory Device and Writing Method Thereof 有权
    非易失性存储器件及其写入方法

    公开(公告)号：US20140219014A1

    公开(公告)日：2014-08-07

    申请号：US14162991

    申请日：2014-01-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang-Woo Lee ,  Daewon Ha

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C13/0064

    Abstract: A writing method of a nonvolatile memory device is provided which receiving data, a target time, and a target resistance value; writing the data at a memory cell; calculating a resistance drift coefficient based on resistance values of the memory cell read on at least two times; calculating a resistance value of the memory cell on the target time using the resistance drift coefficient; and determining whether the resistance value calculated satisfies the target resistance value.

    Abstract translation: 提供了一种非易失性存储器件的写入方法，其接收数据，目标时间和目标电阻值; 将数据写入存储单元; 基于读取的存储器单元的电阻值计算电阻漂移系数至少两次; 使用电阻漂移系数计算目标时间上的存储单元的电阻值; 以及确定所计算的电阻值是否满足目标电阻值。

    Semiconductor devices and methods of manufacturing the same
    6.
    发明授权
    Semiconductor devices and methods of manufacturing the same 有权

    公开(公告)号：US10249820B2

    公开(公告)日：2019-04-02

    申请号：US15366574

    申请日：2016-12-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-Woo Lee ,  Dae-Hwan Kang ,  Gwan-Hyeob Koh

    IPC: H01L27/24 ,  H01L45/00

    Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

    Semiconductor memory device and refresh leveraging driving method thereof
    8.
    发明授权
    Semiconductor memory device and refresh leveraging driving method thereof 有权
    半导体存储器件及其更新利用驱动方法

    公开(公告)号：US08988964B2

    公开(公告)日：2015-03-24

    申请号：US14071757

    申请日：2013-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Jeong Kim ,  Kabyong Kim ,  Kwang-Woo Lee ,  Heon Lee ,  Inho Cho

    IPC: G11C7/22 ,  G11C11/406 ,  G11C16/34 ,  G11C29/00

    CPC classification number: G11C11/40603 ,  G11C11/406 ,  G11C16/3418 ,  G11C29/82 ,  G11C2211/4063

    Abstract: A refresh leveraging driving method is provided which includes deciding a unit of word lines to be driven at a refresh leveraging operation to be the same as a redundancy repair row unit setting a lower row address of an input refresh leveraging address corresponding to the decided refresh leveraging row driving unit to a don't care state; and internally generating the don't care lower row address of the refresh leveraging address to drive word lines according to a combined refresh leveraging address.

    Abstract translation: 提供了一种刷新利用驱动方法，其包括将刷新利用操作中要驱动的字线的单位确定为与冗余修复行单元相同的冗余修复行单元，该冗余修复行单元设置与所决定的刷新利用相对应的输入刷新利用地址的较低行地址 行驱动单位到不关心状态; 并且根据组合的刷新利用地址在内部生成不关心刷新利用地址的较低行地址来驱动字线。

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