公开(公告)号：US20200211907A1

公开(公告)日：2020-07-02

申请号：US16810937

申请日：2020-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul Sun ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  G06F7/505 ,  H01L23/535 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/092 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  G06F30/398 ,  G06F30/39

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20220208616A1

公开(公告)日：2022-06-30

申请号：US17698487

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20190027411A1

公开(公告)日：2019-01-24

申请号：US16144232

申请日：2018-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  G06F7/505 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L29/10 ,  G06F17/50

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20180254219A1

公开(公告)日：2018-09-06

申请号：US15658964

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505

CPC classification number: H01L21/823807 ,  G06F7/505 ,  G06F17/5081 ,  G06F2217/84 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20150054054A1

公开(公告)日：2015-02-26

申请号：US14536250

申请日：2014-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Soo AHN ,  O Ik KWON ,  Bum-Soo KIM ,  Hyun-Sung KIM ,  Kyoung-Sub SHIN ,  Min-Kyung YUN ,  Seung-Pil CHUNG ,  Won-Bong JUNG

IPC: H01L29/788 ,  H01L29/423

CPC classification number: H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在 隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层 以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

公开(公告)号：US20240047275A1

公开(公告)日：2024-02-08

申请号：US18491470

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823871 ,  H01L29/66545 ,  H01L21/30608 ,  H01L21/308 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/0847 ,  H01L29/0653 ,  H01L23/535 ,  G06F7/505 ,  H01L29/41791 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  G06F30/39 ,  G06F30/398 ,  H01L29/66795 ,  G06F2119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.