公开(公告)号：US20220208616A1

公开(公告)日：2022-06-30

申请号：US17698487

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20190027411A1

公开(公告)日：2019-01-24

申请号：US16144232

申请日：2018-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  G06F7/505 ,  H01L29/08 ,  H01L29/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/308 ,  H01L21/306 ,  H01L29/10 ,  G06F17/50

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20240047521A1

公开(公告)日：2024-02-08

申请号：US18488381

申请日：2023-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dae Won HA ,  Dong Hoon HWANG ,  Jong Hwa BAEK ,  Jong Min JEON ,  Seung Mo HA ,  Kwang Yong YANG ,  Jae Young PARK ,  Young Su CHUNG

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L27/0886 ,  H01L21/823431 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/41791

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US20140099793A1

公开(公告)日：2014-04-10

申请号：US14049479

申请日：2013-10-09

Applicant: Seoul National University R&DB Foundation ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Byung-Gook PARK

IPC: H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract translation: 一种制造半导体器件的方法包括：在衬底上形成第一掩模，通过使用第一掩模执行衬底的第一蚀刻形成鳍的第一侧壁，在衬底上形成第二掩模，第二掩模不同 并且通过使用所述第二掩模对所述基板进行第二蚀刻来形成所述翅片的第二侧壁。

公开(公告)号：US20210233995A1

公开(公告)日：2021-07-29

申请号：US17212847

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dae Won HA ,  Dong Hoon HWANG ,  Jong Hwa BAEK ,  Jong Min JEON ,  Seung Mo HA ,  Kwang Yong YANG ,  Jae Young PARK ,  Young Su CHUNG

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US20140035051A1

公开(公告)日：2014-02-06

申请号：US14050469

申请日：2013-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dong-Suk SHIN ,  Jung-Deog LEE

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6656

Abstract: A semiconductor device and process of fabricating the same, the semiconductor device including a semiconductor substrate, a gate insulating layer on the semiconductor substrate, a gate electrode having sidewalls, on the gate insulating layer, first spacers on the sidewalls of the gate electrode, a source/drain region in the semiconductor substrate, aligned with the sidewalls, a silicide layer on the gate electrode, a silicide layer on the source/drain region, and second spacers covering the first spacers and end parts of a surface of the silicide layer on the source drain region.

Abstract translation: 一种半导体器件及其制造方法，半导体器件包括半导体衬底，半导体衬底上的栅极绝缘层，具有侧壁的栅电极，栅极绝缘层，栅电极的侧壁上的第一间隔物， 源极/漏极区域，与侧壁对准，栅极上的硅化物层，源极/漏极区域上的硅化物层，以及覆盖第一间隔物和硅化物层的表面的端部的第二间隔物， 源极漏极区域。

公开(公告)号：US20240047275A1

公开(公告)日：2024-02-08

申请号：US18491470

申请日：2023-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505 ,  H01L29/417 ,  H01L21/8234 ,  H01L27/088 ,  G06F30/39 ,  G06F30/398

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/823871 ,  H01L29/66545 ,  H01L21/30608 ,  H01L21/308 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/0847 ,  H01L29/0653 ,  H01L23/535 ,  G06F7/505 ,  H01L29/41791 ,  H01L21/823431 ,  H01L27/0886 ,  H01L21/823412 ,  H01L21/823418 ,  G06F30/39 ,  G06F30/398 ,  H01L29/66795 ,  G06F2119/12

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.

公开(公告)号：US20140097502A1

公开(公告)日：2014-04-10

申请号：US14048347

申请日：2013-10-08

Applicant: Seoul National University R & DB Foundation ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Byung-Gook PARK

IPC: H01L27/088 ,  H01L29/772

CPC classification number: H01L21/823412 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/02647 ,  H01L21/3065 ,  H01L27/088 ,  H01L27/1222 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/772 ,  H01L29/7843 ,  H01L29/78651 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract translation: 半导体器件具有形成在基板上的各个区域中的栅极全绕器件。 全门设备具有不同级别的纳米线。 第一区域中的栅极全周围器件的阈值电压基于相邻第二区域中的有源层的厚度。 第二区域中的有源层可以处于与第一区域中的纳米线基本相同的水平。 因此，第一区域中的纳米线可以具有基于第二区域中的有源层的厚度的厚度，或者厚度可以不同。 当包括多于一个活性层时，不同区域中的纳米线可以设置在不同的高度和/或可以具有不同的厚度。

公开(公告)号：US20180254219A1

公开(公告)日：2018-09-06

申请号：US15658964

申请日：2017-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Chul SUN ,  Myeong-Cheol KIM ,  Kyoung-Sub SHIN

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  G06F7/505

CPC classification number: H01L21/823807 ,  G06F7/505 ,  G06F17/5081 ,  G06F2217/84 ,  H01L21/30608 ,  H01L21/308 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/66545

Abstract: In a method of manufacturing a semiconductor device, first to third active fins are formed on a substrate. Each of the first to third active fins extends in a first direction, and the second active fin, the first active fin, and the third active fin are disposed in this order in a second direction crossing the first direction. The second active fin is removed using a first etching mask covering the first and third active fins. The third active fin is removed using a second etching mask covering the first active fin and a portion of the substrate from which the second active fin is removed. A first gate structure is formed on the first active fin. A first source/drain layer is formed on a portion of the first active fin adjacent the first gate structure.