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    Memory device for performing internal process and operating method thereof
    3.
    发明授权
    Memory device for performing internal process and operating method thereof 有权

    公开(公告)号：US10262699B2

    公开(公告)日：2019-04-16

    申请号：US16106492

    申请日：2018-08-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Reum Oh ,  Je-Min Ryu ,  Pavan Kumar Kasibhatla

    IPC: G11C5/02 ,  G11C29/48 ,  G11C29/12 ,  G11C7/10 ,  G06F12/0893 ,  G06F12/084 ,  H01L25/18

    Abstract: A memory device includes a memory cell array having a plurality of memory cell groups with a corresponding plurality of independent channels, and the device and an operating method thereof perform an internal data processing operation for the memory cell groups. The memory device includes an internal command generator configured to generate one or more internal commands in order to perform an internal data processing operation in response to a reception of a command, and an internal common bus for a common internal processing channel which is disposed to be shared by the plurality of memory cell groups and configured to form a transmission path of data between the plurality of memory cell groups when the internal data processing operation is performed.

    Repair circuit and fuse circuit
    4.
    发明授权
    Repair circuit and fuse circuit 有权
    维修电路和保险丝电路

    公开(公告)号：US09287009B2

    公开(公告)日：2016-03-15

    申请号：US14595500

    申请日：2015-01-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kyu-Chang Kang ,  Gil-Su Kim ,  Je-Min Ryu ,  Yun-Young Lee ,  Kyo-Min Sohn

    IPC: G11C17/16 ,  G11C29/00 ,  G11C17/18

    CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

    Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

    Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。

    Memory device, method of operating the same, and electronic device having the memory device
    5.
    发明授权
    Memory device, method of operating the same, and electronic device having the memory device 有权
    存储装置，其操作方法和具有存储装置的电子装置

    公开(公告)号：US08897055B2

    公开(公告)日：2014-11-25

    申请号：US13771633

    申请日：2013-02-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

    IPC: G11C17/16 ,  G11C29/00 ,  G11C7/10 ,  G11C17/18

    CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

    Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

    Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

    Stacked memory device and a memory chip including the same
    8.
    发明授权
    Stacked memory device and a memory chip including the same 有权

    公开(公告)号：US10768824B2

    公开(公告)日：2020-09-08

    申请号：US16418502

    申请日：2019-05-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hak-Soo Yu ,  Je-Min Ryu ,  Reum Oh ,  Pavan Kumar Kasibhatla ,  Seok-In Hong

    IPC: G06F3/06 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06

    Abstract: A stacked memory includes a logic semiconductor die, a plurality of memory semiconductor dies stacked with the logic semiconductor die, a plurality of through-silicon vias (TSVs) electrically connecting the logic semiconductor die and the memory semiconductor dies, a global processor disposed in the logic semiconductor die and configured to perform a global sub process corresponding to a portion of a data process, a plurality of local processors respectively disposed in the memory semiconductor dies and configured to perform local sub processes corresponding to other portions of the data process and a plurality of memory integrated circuits respectively disposed in the memory semiconductor dies and configured to store data associated with the data process.

    Fuse data reading circuit having multiple reading modes and related devices, systems and methods
    9.
    发明授权
    Fuse data reading circuit having multiple reading modes and related devices, systems and methods 有权
    具有多种读取模式和相关设备，系统和方法的保险丝数据读取电路

    公开(公告)号：US09343175B2

    公开(公告)日：2016-05-17

    申请号：US13835319

    申请日：2013-03-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Je-Min Ryu ,  Seong-Jin Jang

    IPC: G11C17/00 ,  G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/00

    CPC classification number: G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/789

    Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

    Abstract translation: 熔丝数据读取电路被配置为以多读取模式读取熔丝数据。 熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。 熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。 控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。 方法包括操作和使用熔丝数据读取电路。

    MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE
    10.
    发明申请
    MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE 有权
    存储器件，其操作方法和具有存储器件的电子器件

    公开(公告)号：US20130322149A1

    公开(公告)日：2013-12-05

    申请号：US13771633

    申请日：2013-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

    IPC: G11C17/16 ,  G11C17/18

    CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

    Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

    Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

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