公开(公告)号：US09293218B2

公开(公告)日：2016-03-22

申请号：US14049399

申请日：2013-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Yu ,  Sung-Min Seo ,  Ho-Young Song ,  Gil-Su Kim ,  Jong-Min Oh

IPC: G11C16/04 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

CPC classification number: G11C17/08 ,  G11C16/04 ,  G11C16/0483 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.

Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。

公开(公告)号：US09343175B2

公开(公告)日：2016-05-17

申请号：US13835319

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Je-Min Ryu ,  Seong-Jin Jang

IPC: G11C17/00 ,  G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/00

CPC classification number: G11C17/18 ,  G11C7/14 ,  G11C17/16 ,  G11C29/789

Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.

Abstract translation: 熔丝数据读取电路被配置为以多读取模式读取熔丝数据。 熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。 熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。 控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。 方法包括操作和使用熔丝数据读取电路。

公开(公告)号：US20130322149A1

公开(公告)日：2013-12-05

申请号：US13771633

申请日：2013-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

IPC: G11C17/16 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。

公开(公告)号：US09692424B2

公开(公告)日：2017-06-27

申请号：US14847076

申请日：2015-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gil-Su Kim

IPC: H03K17/16 ,  H03K19/20 ,  H03K19/003

CPC classification number: H03K19/20 ,  H03K19/00346

Abstract: A decoupling circuit and a semiconductor device including the same are provided. The decoupling circuit includes a first circuit including a first capacitor having a first end connected to a first terminal, a first switch device connected between a second end of the first capacitor and a second terminal, and a first control device configured to turn on/off the first switch device based on a voltage level of the a second end of the first capacitor, and a second circuit including a second capacitor having a first end connected to the first terminal, a second switch device connected between a second end of the second capacitor and the second terminal, and a second control device configured to turn on/off the second switch device based on a voltage level of the second end of the second capacitor and an output signal of the first control device.

公开(公告)号：US09287009B2

公开(公告)日：2016-03-15

申请号：US14595500

申请日：2015-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Chang Kang ,  Gil-Su Kim ,  Je-Min Ryu ,  Yun-Young Lee ,  Kyo-Min Sohn

IPC: G11C17/16 ,  G11C29/00 ,  G11C17/18

CPC classification number: G11C29/76 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/78 ,  G11C2029/4402

Abstract: A repair circuit includes first and second fuse circuits, a determination circuit and an output circuit. The first fuse circuit includes a first fuse and is configured to generate a first master signal indicating whether the first fuse has been programmed. The second fuse circuit includes second fuses and is configured to generate a first address indicating whether each of the second fuses has been programmed. The determination circuit is configured to generate a detection signal based on the first master signal and the first address. The detection signal indicates whether a negative program operation has been performed on the second fuse circuit. The output circuit is configured to generate a second master signal based on the first master signal and the detection signal and generate a repair address corresponding to a defective input address based on the first address and the detection signal.

Abstract translation: 修复电路包括第一和第二熔丝电路，确定电路和输出电路。 第一熔丝电路包括第一熔丝，并且被配置为产生指示第一熔丝是否已被编程的第一主信号。 第二熔丝电路包括第二保险丝，并且被配置为产生指示每个第二保险丝是否被编程的第一地址。 确定电路被配置为基于第一主信号和第一地址产生检测信号。 检测信号指示是否对第二熔丝电路执行了负编程操作。 输出电路被配置为基于第一主信号和检测信号产生第二主信号，并且基于第一地址和检测信号产生对应于有缺陷的输入地址的修复地址。

公开(公告)号：US08897055B2

公开(公告)日：2014-11-25

申请号：US13771633

申请日：2013-02-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min Ryu ,  Gil-Su Kim ,  Jong-Min Oh ,  Sung-Min Seo ,  Ho-Young Song ,  Yong-Ho Cho

IPC: G11C17/16 ,  G11C29/00 ,  G11C7/10 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C7/1045 ,  G11C17/18 ,  G11C29/802

Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.

Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。