公开(公告)号：US09368597B2

公开(公告)日：2016-06-14

申请号：US14660191

申请日：2015-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbum Koo ,  Seungjae Lee ,  Shinhye Kim ,  Zulkamain ,  Narae Oh ,  Jeong-Kyu Lee

IPC: H01L21/283 ,  H01L29/66 ,  H01L29/423 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/78 ,  H01L27/11 ,  H01L23/528

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L21/76897 ,  H01L23/528 ,  H01L27/1104 ,  H01L29/165 ,  H01L29/4232 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The methods may include forming a sacrificial gate pattern on a substrate, forming a first spacer on a sidewall of the sacrificial gate pattern and forming a first interlayer dielectric (ILD) layer covering a sidewall of the first spacer and exposing a top surface of the first spacer. The first spacer may expose an upper portion of the sidewall of the sacrificial gate pattern. The methods may also include forming a capping insulating pattern covering top surfaces of the first spacer and the first ILD layer, replacing the sacrificial gate pattern with a gate electrode structure and patterning the capping insulating pattern to form a second spacer on the first spacer and between the gate electrode structure and the first ILD layer. The second spacer may be formed of a material having a dielectric constant higher than a dielectric constant of the first spacer.

Abstract translation: 提供了制造半导体器件的半导体器件和方法。 所述方法可以包括在衬底上形成牺牲栅极图案，在牺牲栅极图案的侧壁上形成第一间隔物，并形成覆盖第一间隔物的侧壁的第一层间电介质（ILD）层，并暴露第一间隔物的顶表面 间隔 第一间隔物可以暴露牺牲栅极图案的侧壁的上部。 所述方法还可以包括形成覆盖第一间隔物和第一ILD层的顶表面的封盖绝缘图案，用栅极电极结构代替牺牲栅极图案，并且图案化封盖绝缘图案以在第一间隔物上形成第二间隔物， 栅电极结构和第一ILD层。 第二间隔物可以由具有高于第一间隔物的介电常数的介电常数的材料形成。

公开(公告)号：US09627509B2

公开(公告)日：2017-04-18

申请号：US14802519

申请日：2015-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungbum Koo ,  Wandon Kim ,  Sangjin Hyun ,  Shinhye Kim ,  TaekSoo Jeon ,  Byung-Suk Jung

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L21/02362 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/51 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/78 ,  H01L2029/7858

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device may include a substrate with an active pattern, a gate electrode provided at the active pattern, and a gate capping structure disposed above the gate electrode. The gate capping structure may include two or more gate capping patterns with different properties from each other, and the use of the gate capping structure makes it possible to form contact plugs in a self-aligned manner and improve operational speed and characteristics of the semiconductor device.