公开(公告)号：US20250040215A1

公开(公告)日：2025-01-30

申请号：US18439634

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Dong Hoon HWANG ,  Hyo Jin KIM ,  Myung II KANG ,  Tae Hyun RYU ,  Kyu Nam PARK ,  Woo Seok PARK

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases. A width of an uppermost portion of the channel isolation structure is greater than a width of a lowermost portion of the channel isolation structure

公开(公告)号：US20200027895A1

公开(公告)日：2020-01-23

申请号：US16272265

申请日：2019-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namkyu Edward CHO ,  Seok Hoon KIM ,  Myung II KANG ,  Geo Myung SHIN ,  Seung Hun LEE ,  Jeong Yun LEE ,  Min Hee CHOI ,  Jeong Min CHOI

IPC: H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

公开(公告)号：US20170133275A1

公开(公告)日：2017-05-11

申请号：US15413472

申请日：2017-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Hae KIM ,  Jin Wook LEE ,  Jong Ki JUNG ,  Myung II KANG ,  Kwang Yong YANG ,  Kwan Heum LEE ,  Byeong Chan LEE

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/08 ,  H01L21/311 ,  H01L27/092 ,  H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.