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    SEMICONDUCTOR DEVICE INCLUDING A GATE STRUCTURE
    2.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING A GATE STRUCTURE 有权

    公开(公告)号：US20220130972A1

    公开(公告)日：2022-04-28

    申请号：US17388269

    申请日：2021-07-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Namgyu Cho ,  Minwoo Song ,  Ohseong Kwon ,  Wandon Kim ,  Hyeokjun Son ,  Jinkyu Jang

    IPC: H01L29/417 ,  H01L29/423 ,  H01L29/78

    Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

    Semiconductor device including a gate structure
    3.
    发明授权
    Semiconductor device including a gate structure 有权

    公开(公告)号：US11594604B2

    公开(公告)日：2023-02-28

    申请号：US17388269

    申请日：2021-07-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Namgyu Cho ,  Minwoo Song ,  Ohseong Kwon ,  Wandon Kim ,  Hyeokjun Son ,  Jinkyu Jang

    IPC: H01L29/417 ,  H01L29/78 ,  H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L29/775 ,  H01L29/66

    Abstract: A semiconductor device includes: an active fin disposed on a substrate; a gate structure overlapping the active fin; source/drain regions disposed on both sides of the gate structure and on the active fin; and contact structures respectively connected to the source/drain regions, wherein the gate structure includes: a pair of gate spacers spaced apart from each other to provide a trench; a first gate electrode disposed in the trench and extending along an upper surface and a lateral surface of the active fin; a second gate electrode disposed on the first gate electrode in the trench, wherein the first gate electrode is not disposed between the second gate electrode and the pair of gate spacers; and a gate insulating film disposed between the pair of gate spacers and interposed between the first gate electrode and the active fin.

    Methods of fabricating semiconductor devices including differing barrier layer structures
    4.
    发明授权
    Methods of fabricating semiconductor devices including differing barrier layer structures 有权

    公开(公告)号：US10804158B2

    公开(公告)日：2020-10-13

    申请号：US16785236

    申请日：2020-02-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

    IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

    Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150311310A1

    公开(公告)日：2015-10-29

    申请号：US14700346

    申请日：2015-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SEOKJUN WON ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28

    CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

    Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

    Methods of fabricating semiconductor devices including differing barrier layer structures
    7.
    发明授权
    Methods of fabricating semiconductor devices including differing barrier layer structures 有权

    公开(公告)号：US10593597B2

    公开(公告)日：2020-03-17

    申请号：US16185213

    申请日：2018-11-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Namgyu Cho ,  Kughwan Kim ,  Geunwoo Kim ,  Jungmin Park ,  Minwoo Song

    IPC: H01L21/82 ,  H01L29/40 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3213

    Abstract: A method of fabricating a semiconductor device may include forming a first conductive layer on first to third regions of a substrate, forming a barrier layer on the first conductive layer, the barrier layer including a first barrier layer, a second barrier layer, and a sacrificial layer which are sequentially formed, sequentially forming a second conductive layer and a third conductive layer on the barrier layer, performing a first etching process to remove the third conductive layer from the second region and the third region, the third conductive layer remaining on the first region after the first etching process, and performing a second etching process to remove the second conductive layer and the sacrificial layer from the third region, the second conductive layer and the sacrificial layer remaining on the first region and on the second region after the second etching process.

    Semiconductor devices and methods for fabricating the same
    9.
    发明授权
    Semiconductor devices and methods for fabricating the same 有权
    半导体器件及其制造方法

    公开(公告)号：US09064723B2

    公开(公告)日：2015-06-23

    申请号：US13751731

    申请日：2013-01-28

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seokjun Won ,  Youngmook Oh ,  Moonkyun Song ,  MinWoo Song ,  Namgyu Cho

    IPC: H01L29/788 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/092

    CPC classification number: H01L29/6656 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823456 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/092 ,  H01L29/6653 ,  H01L29/66553

    Abstract: A semiconductor device includes a substrate including a first region and a second region, a first gate dielectric layer, a first lower gate electrode, and a first upper gate electrode sequentially stacked on the first region, a second gate dielectric layer, a second lower gate electrode, and a second upper gate electrode sequentially stacked on the second region, a first spacer disposed on a sidewall of the first upper gate electrode, a second spacer disposed on a sidewall of the second upper gate electrode, a third spacer covering the first spacer on the sidewall of the first upper gate electrode, and a fourth spacer covering the second spacer on the sidewall of the second upper gate electrode. At least one of a first sidewall of the first lower gate electrode and a second sidewall of the first lower gate electrode is in contact with the third spacer.

    Abstract translation: 半导体器件包括：基板，包括第一区域和第二区域，第一栅极介电层，第一下部栅极电极和顺序堆叠在第一区域上的第一上部栅极电极，第二栅极介电层，第二下部栅极 电极和顺序堆叠在第二区域上的第二上栅电极，设置在第一上栅电极的侧壁上的第一间隔件，设置在第二上栅电极的侧壁上的第二间隔件，覆盖第一间隔件的第三间隔件 在第一上栅极电极的侧壁上，以及覆盖第二上栅电极的侧壁上的第二间隔物的第四间隔件。 第一下栅电极的第一侧壁和第一下栅电极的第二侧壁中的至少一个与第三间隔件接触。

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