公开(公告)号：US11527296B2

公开(公告)日：2022-12-13

申请号：US17232370

申请日：2021-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Yeun Jung ,  Young-Jin Cho ,  Bu-Il Nam ,  Nari Lee ,  Yeji Nam ,  Sangyong Yoon

IPC: G11C16/34 ,  G11C16/24 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16

Abstract: An operation method of a nonvolatile memory device which includes a memory block having wordlines includes performing an erase on the memory block, performing a block verification on the memory block by using a 0-th erase verification voltage, performing a delta verification on the memory block by using a first erase verification voltage different from the 0-th erase verification voltage when a result of the block verification indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification or a result of the delta verification. The delta verification includes generating delta counting values respectively corresponding to wordline groups by using the first erase verification voltage, generating a delta value based on the delta counting values, and comparing the delta value and a first reference value.

公开(公告)号：US11967367B2

公开(公告)日：2024-04-23

申请号：US17806103

申请日：2022-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyu-Ha Park ,  Jeongyeol Kim ,  Nari Lee ,  Daehan Kim

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/54

CPC classification number: G11C11/5628 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3459 ,  G11C29/54

Abstract: Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.

公开(公告)号：US11817158B2

公开(公告)日：2023-11-14

申请号：US18079433

申请日：2022-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Yeun Jung ,  Young-Jin Cho ,  Bu-Il Nam ,  Nari Lee ,  Yeji Nam ,  Sangyong Yoon

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/24 ,  G11C16/10 ,  G11C16/16

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102 ,  G11C16/16 ,  G11C16/24 ,  G11C16/30

Abstract: An operation method of a nonvolatile memory device which includes a memory block having wordlines includes performing an erase on the memory block, performing a block verification on the memory block by using a 0-th erase verification voltage, performing a delta verification on the memory block by using a first erase verification voltage different from the 0-th erase verification voltage when a result of the block verification indicates a pass, and outputting information about an erase result of the memory block based on the result of the block verification or a result of the delta verification. The delta verification includes generating delta counting values respectively corresponding to wordline groups by using the first erase verification voltage, generating a delta value based on the delta counting values, and comparing the delta value and a first reference value.

公开(公告)号：US20230110663A1

公开(公告)日：2023-04-13

申请号：US17806103

申请日：2022-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyu-Ha Park ,  Jeongyeol Kim ,  Nari Lee ,  Daehan Kim

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C29/54

Abstract: Disclosed is a nonvolatile memory device which includes a memory cell array, a row decoder circuit that selects one wordline as a target of a program operation, a page buffer circuit that stores data to be written in memory cells connected with the selected wordline in the program operation, and a pass/fail check circuit that determines a pass or a fail of the program operation. In the program operation, the pass/fail check circuit detects a first program speed of first memory cells and a second program speed of second memory cells, and determines a program fail based on the first program speed and the second program speed.