公开(公告)号：US20150286271A1

公开(公告)日：2015-10-08

申请号：US14678164

申请日：2015-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tushar VRIND ,  Balaji SOMU KANDASWAMY ,  Raju Siddappa UDAVA ,  Venkata Raju INDUKURI

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3228 ,  G06F1/329 ,  Y02D10/171 ,  Y02D10/24

Abstract: A method and system for providing power management in a system employing a Central Processing Unit (CPU) and an operating system are provided. The method includes monitoring idle times of the CPU; predicting an idle pattern based on the monitored idle times; and determining a selective sleep of a peripheral device based on the predicted CPU idle pattern.

Abstract translation: 提供了一种在采用中央处理单元（CPU）和操作系统的系统中提供电源管理的方法和系统。 该方法包括监视CPU的空闲时间; 基于监视的空闲时间预测空闲模式; 以及基于所预测的CPU空闲模式来确定外围设备的选择性睡眠。

公开(公告)号：US20180032376A1

公开(公告)日：2018-02-01

申请号：US15660246

申请日：2017-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raju Siddappa UDAVA ,  Balaji SOMU KANDASWAMY ,  Prasanth SUBRAMANI ,  Tushar VRIND ,  Venkata Raju INDUKURI ,  Diwakar SHARMA

IPC: G06F9/50 ,  G06F9/48

CPC classification number: G06F9/5061 ,  G06F9/4881 ,  G06F9/5038 ,  G06F9/5066 ,  G06F2209/483 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/36

Abstract: A method for group-based scheduling in a multi-core processor apparatus comprises computing a cost of at least two tasks accessing a same resource based on a plurality of parameters; determining, by the multi-core processor apparatus, inter-dependent tasks from among a plurality of tasks based on a plurality of parameters by comparing the computed cost of the at least two tasks with a task inter-dependent threshold; generating, by the multi-core processor apparatus, at least one task group including the inter-dependent tasks; and scheduling, by multi-core processor apparatus, at least one inter-dependent task from the at least one task group on a core of the multi-core processor apparatus.

公开(公告)号：US20230058920A1

公开(公告)日：2023-02-23

申请号：US17876144

申请日：2022-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mallikarjun Shivappa BIDARI ,  Divakar KULKARNI ,  Raju Siddappa UDAVA ,  Shashank VIMAL ,  Tushar VRIND ,  Venkata Raju INDUKURI ,  Harish Kumar Veerappanchatram SUNDARAMURTHY ,  Rajiv HASIJA

IPC: G06F9/52 ,  G06F9/38 ,  G06F9/48

Abstract: A multicore computing device includes a memory and a processor coupled to the memory. The processor includes plural cores and a multiple input multiple output (MIMO) block coupled to the cores. The MIMO block receives a halt request from a first core of the cores, transmits a core-halt request to one or more other cores other than the first core, to halt execution of the one or more other cores, and permits the first core to lock with a shared resource.

公开(公告)号：US20160094955A1

公开(公告)日：2016-03-31

申请号：US14663773

申请日：2015-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vinay Kumar SHRIVASTAVA ,  Raju Siddappa UDAVA

IPC: H04W4/06 ,  H04W72/12

CPC classification number: H04W4/06 ,  H04W72/005

Abstract: A method of Physical Multicast Channel (PMCH) decoding for Multicast Broadcast Single Frequency Network (MBSFN) by a UE includes decoding a Transport Block (TB) in a first sub-frame of a Multicast Channel Scheduling Period (MSP) by a Physical (PHY) layer in the UE; providing the decoded TB to a Media Access Control (MAC) layer; performing blind decoding on all received MBSFN sub-frames, until the PHY layer receives PMCH scheduling configuration from the MAC layer; selecting at least one Logical Channel IDentifier (LCID) and Multicast Transport Channel (MTCH) scheduling information for each LCID by decoding a Multicast Channel Scheduling Information Protocol Data Unit (MSI PDU), the MSI PDU present in the decoded TB; building a PMCH scheduling configuration by the MAC layer based on the selected at least one LCID and the MTCH scheduling information; passing the PMCH scheduling configuration to the PHY layer by the MAC layer; and applying the PMCH scheduling configuration.

Abstract translation: 用于MBMS的组播广播单频网（MBSFN）的物理组播信道（PMCH）解码的方法包括通过物理（PHY）对多播信道调度周期（MSP）的第一子帧中的传输块（TB）进行解码 ）层; 将解码的TB提供给媒体访问控制（MAC）层; 对所有接收的MBSFN子帧执行盲解码，直到PHY层从MAC层接收PMCH调度配置; 通过解码多播信道调度信息协议数据单元（MSI PDU），解码的TB中存在的MSI PDU来为每个LCID选择至少一个逻辑信道标识符（LCID）和组播传输信道（MTCH）调度信息; 基于所选择的至少一个LCID和所述MTCH调度信息，由所述MAC层构建PMCH调度配置; 通过MAC层将PMCH调度配置传递到PHY层; 并应用PMCH调度配置。

公开(公告)号：US20180203722A1

公开(公告)日：2018-07-19

申请号：US15825472

申请日：2017-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raju Siddappa UDAVA ,  Balaji SOMU KANDASWAMY ,  Patana Bhagwan REDDY ,  Tushar VRIND ,  Venkata Raju INDUKURI

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/463 ,  G06F9/461 ,  G06F9/462 ,  G06F9/4812 ,  G06F9/4843

Abstract: The various embodiments of the present invention disclose a method for reducing interrupt latency in embedded systems. According to at least one example embodiment of the inventive concepts, the method for reducing interrupt latency in embedded systems, the method comprises steps of toggling, by a processor, from a supervisor (SVC) mode to an interrupt request (IRQ) mode on receiving an interrupt, identifying, by the processor, a Task Control Block (TCB) of a preempted task on receiving the interrupt, enabling, by the processor, the IRQ stack as a pseudo preempted task context table, and storing the preempted task context information in the IRQ stack, wherein a register set is stored in IRQ stack before processing the received interrupt.

公开(公告)号：US20170212852A1

公开(公告)日：2017-07-27

申请号：US15418249

申请日：2017-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Balaji SOMU KANDASWAMY ,  Patana Bhagwan REDDY ,  Raju Siddappa UDAVA ,  Tushar VRIND ,  Venkata Raju INDUKURI

IPC: G06F13/24 ,  G06F9/54

CPC classification number: G06F13/24 ,  G06F9/542

Abstract: An apparatus and method are provided for interrupt handling. A method includes receiving, by an accelerator unit, an interrupt request; stacking, by the accelerator unit, a plurality of general purpose registers in an inbuilt last in first out (LIFO) unit; and sending, by the accelerator unit, a vector address corresponding to the interrupt request to a processor, which processes the interrupt request.

公开(公告)号：US20150277977A1

公开(公告)日：2015-10-01

申请号：US14676366

申请日：2015-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tushar VRIND ,  Balaji SOMU KANDASWAMY ,  Raju Siddappa UDAVA ,  Venkata Raju INDUKURI

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/461 ,  G06F9/5011 ,  G06F9/5016

Abstract: A method and system for providing memory management in a Real-Time Operating System (RTOS) based system are provided. The method includes creating a plurality of tasks with a two level stack scheme comprising a first level stack and a second level stack, scheduling a first task for execution by moving a stack pointer from the first level stack to the second level stack, determining whether the first task is pre-empted, allocating the second level stack to the first task in a second state if the first task is not pre-empted, changing an active task for execution, determining whether the first task relinquishes control from the second state and is waiting for a resource, moving the stack pointer back from the second level stack to the first level stack if the first task relinquishes itself and providing the second level stack for use by a second task.

Abstract translation: 提供了一种用于在基于实时操作系统（RTOS）的系统中提供存储器管理的方法和系统。 该方法包括通过包括第一级堆栈和第二级堆栈的两级堆栈方案来创建多个任务，通过将堆栈指针从第一级堆栈移动到第二级堆栈来调度第一任务以执行，确定是否 首先任务被抢占，如果第一任务没有被抢占，则将第二级堆栈分配给第一任​​务，改变要执行的活动任务，确定第一任务是否从第二状态放弃控制，并且是第 等待资源，如果第一个任务放弃自身并提供第二级堆栈供第二个任务使用，则将堆栈指针从第二级堆栈移回到第一级堆栈。