公开(公告)号：US20180090589A1

公开(公告)日：2018-03-29

申请号：US15820171

申请日：2017-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Kooktae Kim ,  Chanjin Park ,  Dongsuk Shin ,  Youngdal Lim ,  Sahwan Hong

IPC: H01L29/49 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

公开(公告)号：US11695046B2

公开(公告)日：2023-07-04

申请号：US17370551

申请日：2021-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sahwan Hong ,  Hanki Lee ,  Jeongmin Lee

IPC: H01L29/167 ,  H01L29/08 ,  H01L29/417 ,  H01L21/02 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/8234

CPC classification number: H01L29/167 ,  H01L29/0847 ,  H01L29/41775

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

公开(公告)号：US20230076270A1

公开(公告)日：2023-03-09

申请号：US17720880

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Sunguk Jang ,  Bongjin Kuh ,  Kongsoo Lee ,  Sahwan Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786

Abstract: An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

公开(公告)号：US09865698B2

公开(公告)日：2018-01-09

申请号：US15053842

申请日：2016-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun-Kwan Yu ,  Kooktae Kim ,  Chanjin Park ,  Dongsuk Shin ,  Youngdal Lim ,  Sahwan Hong

IPC: H01L27/108 ,  H01L29/49 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/4991 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes a gate assembly disposed on a device isolation layer, a gate spacer disposed on a side surface of the gate assembly, a contact assembly disposed on the gate spacer, an air gap disposed between the device isolation layer and the contact assembly, and a first spacer capping layer disposed between the gate spacer and the air gap. The first spacer capping layer has an etch selectivity with respect to the gate spacer.

公开(公告)号：US12148800B2

公开(公告)日：2024-11-19

申请号：US18325335

申请日：2023-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sahwan Hong ,  Hanki Lee ,  Jeongmin Lee

IPC: H01L29/167 ,  B82Y10/00 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

公开(公告)号：US20230171950A1

公开(公告)日：2023-06-01

申请号：US17940323

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kongsoo Lee ,  Sahwan Hong

IPC: H01L27/108

CPC classification number: H01L27/10814

Abstract: A semiconductor device includes a plurality of semiconductor patterns stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of a substrate, and extending in a second direction, parallel to the upper surface of the substrate, a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns, a plurality of second conductive patterns extending in the first direction on the substrate, a plurality of capacitors electrically connected to the plurality of semiconductor patterns, respectively, and at least one epitaxial layer disposed to be in contact with at least one of both end surfaces of at least one of the plurality of semiconductor patterns and including an impurity.