公开(公告)号：US11488877B2

公开(公告)日：2022-11-01

申请号：US16191881

申请日：2018-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Chul Sagong ,  June Kyun Park ,  Hyun Jin Kim ,  Ki Hyun Choi ,  Sang Woo Pae

IPC: H01L21/66 ,  H01L27/088 ,  H01L27/11 ,  H01L29/78

Abstract: A semiconductor device including a test structure includes a semiconductor substrate and a plurality of test structures on the semiconductor substrate. The test structures include respective lower active regions extending from the semiconductor substrate in a vertical direction and having different widths, and upper active regions extending from respective lower active regions in the vertical direction. Each of the lower active regions includes first regions and second regions. The first regions overlap the upper active regions and are between the second regions, and the second regions include outer regions and inner regions between the outer regions. The outer regions, located in the lower active regions having different widths, have different widths.

公开(公告)号：US10943900B2

公开(公告)日：2021-03-09

申请号：US16395841

申请日：2019-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Chul Sagong ,  Sang Woo Pae ,  Ki Hyun Choi ,  June Kyun Park ,  Uk Jin Jung

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device is provided. The Semiconductor device includes a substrate, a first fin type pattern and a second fin type pattern which protrude from an upper surface of the substrate and are spaced apart from each other, a first semiconductor pattern on the first fin type pattern, a second semiconductor pattern on the second tin type pattern and a blocking pattern between the first semiconductor pattern and the second semiconductor pattern, a part of the first semiconductor pattern being inserted in the blocking pattern.

公开(公告)号：US11563002B2

公开(公告)日：2023-01-24

申请号：US16418366

申请日：2019-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin Woo Kim ,  Choelhwyi Bae ,  Yang Gyeom Kim ,  Sung Eun Kim ,  Sang Woo Pae ,  Hyun Chui Sagong

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/40 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/765 ,  H01L29/49

Abstract: A semiconductor device includes a first fin that protrudes from a substrate and extends in a first direction, a second fin that protrudes from the substrate and extends in the first direction, the first fin and the second fin being spaced apart, a gate line including a dummy gate electrode and a gate electrode, the dummy gate electrode at least partially covering the first fin, the gate electrode at least partially covering the second fin, the dummy gate electrode including different materials from the gate electrode, the gate line covering the first fin and the second fin, the gate line extending in a second direction different from the first direction, and a gate dielectric layer between the gate electrode and the second fin.

公开(公告)号：US11245018B2

公开(公告)日：2022-02-08

申请号：US16415633

申请日：2019-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Chul Sagong ,  Sung Eun Kim ,  Jin Woo Kim ,  June Kyun Park ,  Sang Woo Pae ,  Ki Hyun Choi

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84

Abstract: A semiconductor device may include an active region extending primarily in a first direction on a substrate. A gate structure may be disposed to intersect the active region, and extend primarily in a second direction intersecting the first direction. A gate isolation pattern may contact one end of the gate structure. The gate structure may include a plurality of portions each having different widths in the first direction, and the gate isolation pattern may have a width greater than a width of at least one of the plurality of portions of the gate structure.

公开(公告)号：US10157259B2

公开(公告)日：2018-12-18

申请号：US15407365

申请日：2017-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong Min Jo ,  Yoo Hwan Kim ,  Hye Won Shim ,  Sang Woo Pae

IPC: G06F17/50 ,  G01R31/28

Abstract: A method for predicting a failure rate of a semiconductor integrated circuit includes receiving a circuit netlist corresponding to circuit defining data, which defines a connection relation, input, output, size, type and operating temperature of each transistor of a plurality of transistors included in the semiconductor integrated circuit. Low-risk transistors having a low-failure probability among the plurality of transistors are detected and filtered out based on the circuit netlist. Failure rates are calculated of respective high-risk transistors other than the low-risk transistors among the plurality of transistors. A total failure rate of the semiconductor integrated circuit is calculated based on the failure rates of the respective high-risk transistors.

公开(公告)号：US09892977B2

公开(公告)日：2018-02-13

申请号：US15270502

申请日：2016-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Woo Pae ,  Hyun Chul Sagong ,  Jin Ju Kim ,  June Kyun Park

IPC: H01L21/82 ,  H01L21/30 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.

公开(公告)号：US20170140997A1

公开(公告)日：2017-05-18

申请号：US15270502

申请日：2016-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Woo Pae ,  Hyun Chul Sagong ,  Jin Ju Kim ,  June Kyun Park

IPC: H01L21/8238 ,  H01L21/308 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of generating a fin of a FinFET includes depositing a first hard mask layer on or above a first dummy gate and a second dummy gate, generating first spacers and second spacers by etching the first hard mask layer, removing only the first spacers, depositing a second hard mask layer, generating third spacers and fourth spacers by etching the second hard mask layer, removing the first dummy gate and the second dummy gate, generating first fins using the third spacers, and generating second fins using the second spacers and the fourth spacers.