公开(公告)号：US20210407577A1

公开(公告)日：2021-12-30

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US11301399B2

公开(公告)日：2022-04-12

申请号：US16934497

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US11152053B2

公开(公告)日：2021-10-19

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4076

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US11860803B2

公开(公告)日：2024-01-02

申请号：US17685987

申请日：2022-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Jaeyoun Youn

IPC: G06F13/38 ,  G06F13/16 ,  H01L25/065 ,  G11C8/10 ,  G11C7/10

CPC classification number: G06F13/1668 ,  H01L25/0657 ,  G11C7/10 ,  G11C8/10 ,  H01L2225/06541

Abstract: A memory device includes a buffer die configured to receive a first broadcast command and a second broadcast command from an external device; and a plurality of core dies stacked on the buffer die. The plurality of core dies include: a first core die including a first processing circuit, a first memory cell array, a first command decoder configured to decode the first broadcast command, and a first data input/output circuit configured to output data of the first memory cell array to a common data input/output bus under control of the first command decoder; and a second core die including a second processing circuit, a second memory cell array, a second command decoder configured to decode the second broadcast command, and a second data input/output circuit configured to receive the data of the first memory cell array through the common data input/output bus under control of the second command decoder.

公开(公告)号：US11763876B2

公开(公告)日：2023-09-19

申请号：US17475479

申请日：2021-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C8/12 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4094 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC classification number: G11C11/4087 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/40618

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US20210217461A1

公开(公告)日：2021-07-15

申请号：US16994796

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

公开(公告)号：US10134487B2

公开(公告)日：2018-11-20

申请号：US14713140

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyuk Kwon ,  Young-Hoon Son ,  Jung-Ho Ahn

IPC: G11C29/00 ,  G09C1/00 ,  H04L9/06 ,  G06F11/07 ,  G06F11/20 ,  G06F11/10 ,  G06F12/02 ,  G06F17/30 ,  G06F12/0802 ,  G11C29/44

Abstract: A memory device may include a memory cell array, a bloom-filter circuit, a cache memory circuit, and a selecting circuit. The bloom-filter circuit may be configured to output a determination result signal that indicates that there is a possibility that a received address is one of failed addresses corresponding to failed cells of the memory cell array. The cache memory circuit may be configured to, store the failed addresses and a first set of data corresponding to the respective failed addresses, and configured to, when the determination result signal indicates a possibility, provide a comparison result signal by determining whether received address coincides with one of the failed addresses. The selecting circuit may be configured to output either first data of the first set of data or second data of the memory cell array corresponding to the received address based on determination result signal and comparison result signal.