公开(公告)号：US09305899B2

公开(公告)日：2016-04-05

申请号：US14640464

申请日：2015-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yong Park ,  Jun-Young Ko ,  Sang-Jun Kim

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/95 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/1182 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Abstract translation: 制造半导体封装的方法包括提供包括具有通过硅通孔（TSV）的上部区域和不具有TSV的下部区域的晶片; 将半导体芯片安装在晶片的上部区域上; 将钝化层形成为预定厚度以覆盖半导体芯片; 在没有支撑件附接到晶片的状态下去除晶片的下部区域来暴露TSV; 以及通过部分去除钝化层来暴露半导体芯片的顶表面。