公开(公告)号：US09305899B2

公开(公告)日：2016-04-05

申请号：US14640464

申请日：2015-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Yong Park ,  Jun-Young Ko ,  Sang-Jun Kim

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L25/00

CPC classification number: H01L24/95 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/1182 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/83

Abstract: A method of fabricating a semiconductor package includes providing a wafer which includes an upper area having through silicon vias (TSVs) and a lower area not having the TSVs; mounting a semiconductor chip on the upper area of the wafer; forming a passivation layer to a predetermined thickness to cover the semiconductor chip; exposing the TSVs by removing the lower area of the wafer in a state where no support is attached to the wafer; and exposing a top surface of the semiconductor chip by partially removing the passivation layer.

Abstract translation: 制造半导体封装的方法包括提供包括具有通过硅通孔（TSV）的上部区域和不具有TSV的下部区域的晶片; 将半导体芯片安装在晶片的上部区域上; 将钝化层形成为预定厚度以覆盖半导体芯片; 在没有支撑件附接到晶片的状态下去除晶片的下部区域来暴露TSV; 以及通过部分去除钝化层来暴露半导体芯片的顶表面。

公开(公告)号：US09255959B2

公开(公告)日：2016-02-09

申请号：US13961201

申请日：2013-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Sik Kwon ,  Seok-Won Jeong ,  Jae-Ho Choi ,  Jun-Young Ko

IPC: G01N23/04 ,  G01R31/26 ,  G01R31/28 ,  G01R31/308

CPC classification number: G01R31/2607 ,  G01N23/04 ,  G01R31/2896 ,  G01R31/308

Abstract: A test apparatus for a semiconductor package comprising an X-ray analyzer acquiring an X-ray image of the semiconductor package and detecting a thickness of the semiconductor package from the X-ray image, and a thermal reaction analyzer applying a voltage to the semiconductor package and detecting a failure position of the semiconductor package using a surface temperature of the semiconductor package and the thickness of the semiconductor package may be provided.

Abstract translation: 一种半导体封装的测试装置，包括：X射线分析仪，获取半导体封装的X射线图像，并从X射线图像检测半导体封装的厚度，以及向半导体封装施加电压的热反应分析器 并且可以提供使用半导体封装的表面温度和半导体封装的厚度来检测半导体封装的故障位置。

公开(公告)号：US08956923B2

公开(公告)日：2015-02-17

申请号：US13835749

申请日：2013-03-15

Applicant: Samsung Electronics Co, Ltd.

Inventor： Young-Ja Kim ,  Jun-Young Ko ,  Dae-Young Jeong ,  Dae-Sang Chan

IPC: H01L21/00 ,  B05C13/02 ,  B29C65/00 ,  B05D5/12 ,  H01L21/56

CPC classification number: H01L21/56 ,  H01L21/563 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device comprises loading a circuit board including a semiconductor chip into underfill equipment, positioning the circuit board on a depositing chuck of the underfill equipment, filling an underfill material in a space between the semiconductor chip and the circuit board placed on the depositing chuck; transferring the circuit board including the underfill material so that it is positioned on a post-treatment chuck of the underfill equipment; heating the underfill material of the circuit board placed on the post-treatment chuck in a vacuum state, and unloading the circuit board, of which the underfill material has been heated in the vacuum state, from the underfill equipment.

Abstract translation: 一种制造半导体器件的方法包括将包括半导体芯片的电路板加载到底部填充设备中，将电路板定位在底部填充设备的沉积卡盘上，在半导体芯片和放置在半导体芯片之间的电路板之间的空间中填充底部填充材料 沉积卡盘; 传送包括底部填充材料的电路板，使其位于底部填充设备的后处理卡盘上; 在真空状态下加热放置在后处理卡盘上的电路板的底部填充材料，并将底部填充材料在真空状态下被加热的电路板从底部填充设备卸载。