公开(公告)号：US11948903B2

公开(公告)日：2024-04-02

申请号：US18119397

申请日：2023-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Seon Gyo Kim ,  Joon Ho Jun

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/17 ,  H01L23/481 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/05 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0233 ,  H01L2224/02372 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05078 ,  H01L2224/05562 ,  H01L2224/06158 ,  H01L2224/06182 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/14152 ,  H01L2224/1416 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.

公开(公告)号：US20240162184A1

公开(公告)日：2024-05-16

申请号：US18337113

申请日：2023-06-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Min Soo Kim ,  Seon Gyo Kim

IPC: H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L24/33 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/3003 ,  H01L2224/30505 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/3303 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/0665 ,  H01L2924/067 ,  H01L2924/07025 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: A semiconductor package includes a first structure, a first semiconductor chip on the first structure, a first conductive pad on the first structure between the first structure and the first semiconductor chip, a second conductive pad on a lower surface of the first semiconductor chip and vertically overlapping the first conductive pad, a bump connecting the first conductive pad and the second conductive pad, a first adhesive layer surrounding at least a part of side walls of the bump and side walls of the first conductive pad, and a second adhesive layer surrounding at least a part of the side walls of the bump and side walls of the second conductive pad, the second adhesive layer including a material different from the first adhesive layer, wherein a horizontal width of the first adhesive layer is smaller than a horizontal width of the second adhesive layer.

公开(公告)号：US11616039B2

公开(公告)日：2023-03-28

申请号：US17220299

申请日：2021-04-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Sick Park ,  Un-Byoung Kang ,  Seon Gyo Kim ,  Joon Ho Jun

IPC: H01L23/48 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor package including a first stack; a plurality of TSVs passing through the first stack; a second stack on the first stack and including a second surface facing a first surface of the first stack; a first pad on the first stack and in contact with the TSVs; a second pad on the second stack; a bump connecting the first and second pads; a first redundancy pad on the first surface of the first stack, spaced apart from the first pad, and not in contact with the TSVs; a second redundancy pad on the second surface of the second stack and spaced apart from the second pad; and a redundancy bump connecting the first redundancy pad and the second redundancy pad, wherein the first pad and first redundancy pad are electrically connected to each other, and the second pad and second redundancy pad are electrically connected to each other.