公开(公告)号：US20230299086A1

公开(公告)日：2023-09-21

申请号：US17956191

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Yong YU ,  Seung Geun JUNG

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device may include an active pattern on a substrate, a lower channel pattern on the active pattern and including first and second lower semiconductor patterns, an upper channel pattern on the lower channel pattern and including first and second upper semiconductor patterns, a pair of lower source/drain patterns on opposite sides of the lower channel pattern and a pair of upper source/drain patterns on opposite sides of the upper channel pattern, and a gate electrode surrounding the lower and upper channel patterns. The gate electrode may include a first upper portion between the first and second upper semiconductor patterns, and a first lower portion between the first and second lower semiconductor patterns. Each semiconductor pattern may include a first recess part having a first recess region on a top surface thereof, and a first protrusion part protruding from a bottom surface of the first recess part.

公开(公告)号：US20240332378A1

公开(公告)日：2024-10-03

申请号：US18463488

申请日：2023-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggwon KIM ,  Seung Geun JUNG ,  Myung Gil KANG ,  Gyeom KIM ,  Dongwon KIM

IPC: H01L29/417 ,  H01L21/768 ,  H01L23/522 ,  H01L29/08 ,  H01L29/40

CPC classification number: H01L29/41733 ,  H01L21/76805 ,  H01L23/5226 ,  H01L29/0847 ,  H01L29/401 ,  H01L23/53295 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device may include a substrate, a lower pattern on the substrate, a channel pattern on the lower pattern, a source/drain pattern on both sides of the channel pattern, a gate structure surrounding the channel pattern, a contact electrode electrically connected to the source/drain pattern, an etch stop layer between the gate structure and the contact electrode, and a contact interface layer on the source/drain pattern. The contact interface layer may include a first region between the source/drain pattern and the contact electrode and a second region between the source/drain pattern and the etch stop layer.