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1.发明授权公开(公告)号：US11927879B2
公开(公告)日：2024-03-12
申请号：US17407642
申请日：2021-08-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Moosong Lee , Seung Yoon Lee , Jeongjin Lee
CPC classification number: G03F1/22 , G03F1/24 , G03F1/42 , G03F7/2004 , G03F7/2022 , G03F9/7003 , G03F9/7084
Abstract: A method includes forming a first photomask including N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions, forming a second photomask including M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions, performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer. The first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M is two times N.
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2.发明申请公开(公告)号：US20220100077A1
公开(公告)日：2022-03-31
申请号：US17407642
申请日：2021-08-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Moosong Lee , Seung Yoon Lee , Jeongjin Lee
Abstract: A method includes forming a first photomask including N mask chip regions and a first mask scribe lane region surrounding each of the N mask chip regions, forming a second photomask including M mask chip regions and a second mask scribe lane region surrounding each of the M mask chip regions, performing a first semiconductor process including a first photolithography process using the first photomask on a semiconductor wafer; and performing a second semiconductor process including a second photolithography process using the second photomask on the semiconductor wafer. The first photolithography process is an extreme ultraviolet (EUV) photolithography process, the first photomask is an EUV photomask, N is a natural number of 2 or more, and M is two times N.
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公开(公告)号：US10119811B2
公开(公告)日：2018-11-06
申请号：US15448325
申请日：2017-03-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Yoon Lee , Chan Hwang , Jeong Jin Lee
Abstract: A method for measuring wafer alignment is provided. The method includes providing a plurality of first mark patterns extending in a first direction on a wafer, providing at least one second mark pattern on the first mark patterns such that it overlaps and intersects the first mark patterns, irradiating an optical signal onto the first mark patterns and the second mark pattern and obtaining coordinates of the second mark pattern by detecting signals from the second mark pattern.
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公开(公告)号：US09846359B1
公开(公告)日：2017-12-19
申请号：US15392297
申请日：2016-12-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seung Hwa Oh , Seung Yoon Lee , Jeong Jin Lee
CPC classification number: G03F1/44 , G01B11/005 , G03F1/36 , G03F1/42 , G03F7/70633 , G03F7/70683 , H01L21/0273 , H01L22/12 , H01L22/20 , H01L22/30
Abstract: A method may include forming a first grating and a second grating, disposed in a region of vertical overlap of the first and second gratings on different levels, respectively, having substantially the same pitch, and inclined with respect to each other, such that a bias value between the first and second gratings is changed along a length direction of the first and second gratings, using a lithography process. A method may include emitting a beam to the first and second gratings; and obtaining trend information associated with a diffracted beam from an image pattern of a beam from the first and second gratings, using the emitted beam, in which the trend information may concern changes in the intensity of the diffracted beam according to the bias value. An overlay error in at least one grating may be determined based on the trend information and an intensity of a diffracted beam.
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