IINTEGRATED CIRCUIT DEVICE INCLUDING ASYMMETRICAL FIN FIELD-EFFECT TRANSISTOR

    公开(公告)号:US20190273153A1

    公开(公告)日:2019-09-05

    申请号:US16417973

    申请日:2019-05-21

    Abstract: An integrated circuit device includes: a first fin active region extending in a first direction parallel to a top surface of a substrate; a second fin active region extending in the first direction and spaced apart from the first fin active region in a second direction different from the first direction; a gate line intersecting the first and second fin active regions; a first source/drain region on one side of the gate line in the first fin active region; and a second source/drain region on one side of the gate line in the second fin active region and facing the first source/drain region, wherein a cross-section of the first source/drain region perpendicular to the first direction has an asymmetric shape with respect to a center line of the first source/drain region in the second direction extending in a third direction perpendicular to the top surface of the substrate.

    IINTEGRATED CIRCUIT DEVICE INCLUDING ASYMMETRICAL FIN FIELD-EFFECT TRANSISTOR

    公开(公告)号:US20190067455A1

    公开(公告)日:2019-02-28

    申请号:US15870549

    申请日:2018-01-12

    Abstract: An integrated circuit device includes: a first fin active region extending in a first direction parallel to a top surface of a substrate; a second fin active region extending in the first direction and spaced apart from the first fin active region in a second direction different from the first direction; a gate line intersecting the first and second fin active regions; a first source/drain region on one side of the gate line in the first fin active region; and a second source/drain region on one side of the gate line in the second fin active region and facing the first source/drain region, wherein a cross-section of the first source/drain region perpendicular to the first direction has an asymmetric shape with respect to a center line of the first source/drain region in the second direction extending in a third direction perpendicular to the top surface of the substrate.

    AUTOMATIC DETECTION METHOD OF VIDEO WALL ARRANGEMENT AND VIDEO WALL SYSTEM USING THE SAME
    7.
    发明申请
    AUTOMATIC DETECTION METHOD OF VIDEO WALL ARRANGEMENT AND VIDEO WALL SYSTEM USING THE SAME 有权
    视频墙布置的自动检测方法和使用其的视频墙系统

    公开(公告)号:US20130293443A1

    公开(公告)日:2013-11-07

    申请号:US13710734

    申请日:2012-12-11

    Abstract: An automatic detection method of an arrangement of a video wall including a plurality of monitors and a video wall system are provided. The method includes: calling, by a control computer, identification information of a first monitor of the plurality of monitors; sending, by the first monitor, a response signal to the control computer and sending, by a second monitor which does not correspond to the called identification information, a detecting signal including a received direction of the response signal to the control computer; and receiving, by the control computer, the detecting signal, and determining the arrangement of the plurality of monitors according to the received detecting signal.

    Abstract translation: 提供了包括多个监视器和视频墙系统的视频墙的布置的自动检测方法。 该方法包括:由控制计算机调用多个监视器的第一监视器的识别信息; 由所述第一监视器向所述控制计算机发送响应信号,并通过与所述被叫识别信息不对应的第二监视器向所述控制计算机发送包括响应信号的接收方向的检测信号; 以及由所述控制计算机接收所述检测信号,以及根据所接收的检测信号确定所述多个监视器的配置。

    INTEGRATED CIRCUIT DEVICES AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20200266101A1

    公开(公告)日:2020-08-20

    申请号:US16868811

    申请日:2020-05-07

    Abstract: An integrated circuit device includes a fin-type active region extending on a substrate in a first direction parallel to a top surface of the substrate; a gate structure extending on the fin-type active region and extending in a second direction parallel to the top surface of the substrate and different from the first direction; and source/drain regions in a recess region extending from one side of the gate structure into the fin-type active region, the source/drain regions including an upper semiconductor layer on an inner wall of the recess region, having a first impurity concentration, and including a gap; and a gap-fill semiconductor layer, which fills the gap and has a second impurity concentration that is greater than the first impurity concentration.

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