公开(公告)号：US11988712B2

公开(公告)日：2024-05-21

申请号：US17551974

申请日：2021-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chunghee Kim ,  Ahreum Kim ,  Minsu Kim ,  Seungman Lim

IPC: G01R31/3185

CPC classification number: G01R31/318541

Abstract: A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

公开(公告)号：US20210334449A1

公开(公告)日：2021-10-28

申请号：US17225773

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/398 ,  H01L23/528 ,  H01L29/423 ,  G06F30/392 ,  G06F30/3953

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US12019965B2

公开(公告)日：2024-06-25

申请号：US17225773

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/528 ,  H01L29/423 ,  G06F117/12

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US20210184038A1

公开(公告)日：2021-06-17

申请号：US16893549

申请日：2020-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungman Lim ,  Jaeho Park ,  Sanghoon Baek ,  Jisu YU ,  Hyeongyu You ,  Seungyoung Lee

IPC: H01L29/78 ,  H01L23/522

Abstract: A semiconductor device includes first and second active patterns, a first gate structure, first and second channels, and first and second source/drain layers. The first and second active patterns extend in a first direction, and are spaced apart in a second direction. The first gate structure extends in the second direction on the first and second active patterns. The first channels are spaced apart in a third direction on the first active pattern. The second channels are spaced apart in the third direction on the second active pattern. The first source/drain layer having a first conductivity type is formed at a side of the first gate structure to contact the first channels. The second source/drain layer having a second conductivity type is formed at a side of the first gate structure to contact the second channels. Widths in the second direction of the first and second channels are different.

公开(公告)号：US12147751B2

公开(公告)日：2024-11-19

申请号：US17360355

申请日：2021-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman Lim ,  Hakchul Jung ,  Sanghoon Baek ,  Jaewoo Seo ,  Jisu Yu ,  Hyeongyu You

IPC: G06F30/3953 ,  G06F30/327 ,  G06F119/06 ,  H01L23/528

Abstract: An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

公开(公告)号：US20240303410A1

公开(公告)日：2024-09-12

申请号：US18670009

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  G06F117/12 ,  H01L23/528 ,  H01L29/423

CPC classification number: G06F30/392 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5283 ,  H01L23/5286 ,  H01L29/42376 ,  G06F2117/12

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US11901902B2

公开(公告)日：2024-02-13

申请号：US17696086

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman Lim ,  Minsu Kim ,  Ahreum Kim

IPC: H03K3/02 ,  H03K3/037 ,  H03K17/687 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H03K3/3562 ,  H03K17/6872

Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.