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    Integrated circuit including asymmetric power line and method of designing the same
    3.
    发明授权
    Integrated circuit including asymmetric power line and method of designing the same 有权

    公开(公告)号：US11755809B2

    公开(公告)日：2023-09-12

    申请号：US17458948

    申请日：2021-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jisu Yu ,  Jaewoo Seo ,  Hyeongyu You ,  Sanghoon Baek ,  Jonghoon Jung

    IPC: G06F30/00 ,  G06F30/392 ,  H01L23/50 ,  H01L27/02

    CPC classification number: G06F30/392 ,  H01L23/50 ,  H01L27/0207

    Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS
    5.
    发明公开
    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20230297752A1

    公开(公告)日：2023-09-21

    申请号：US18162120

    申请日：2023-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Sanghoon Baek

    IPC: G06F30/392

    CPC classification number: G06F30/392

    Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.

    INTEGRATED CIRCUIT INCLUDING MULTI-HEIGHT CELLS AND METHOD OF DESIGNING THE SAME
    9.
    发明公开
    INTEGRATED CIRCUIT INCLUDING MULTI-HEIGHT CELLS AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20230378156A1

    公开(公告)日：2023-11-23

    申请号：US18303607

    申请日：2023-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeongyu You ,  Jisu Yu ,  Geonwoo Nam ,  Jungho Do ,  Minjae Jeong ,  Jaehee Cho

    IPC: H01L27/02 ,  G06F30/31

    CPC classification number: H01L27/0207 ,  G06F30/31

    Abstract: An integrated circuit includes a first cell and a second cell respectively arranged in a first row and a second row that are adjacent to each other and extend in a first direction, and a third cell continuously arranged in the first row and the second row, wherein each of the first cell and the second cell comprises a first active pattern group including at least one active pattern that extends in the first direction and has a first conductivity type, the third cell comprises a second active pattern group including at least one active pattern that extends in the first direction in the first row and has the first conductivity type, and an effective channel width of the second active pattern group is greater than an effective channel width of the first active pattern group.

    SEMICONDUCTOR DEVICES
    10.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20210184038A1

    公开(公告)日：2021-06-17

    申请号：US16893549

    申请日：2020-06-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seungman Lim ,  Jaeho Park ,  Sanghoon Baek ,  Jisu YU ,  Hyeongyu You ,  Seungyoung Lee

    IPC: H01L29/78 ,  H01L23/522

    Abstract: A semiconductor device includes first and second active patterns, a first gate structure, first and second channels, and first and second source/drain layers. The first and second active patterns extend in a first direction, and are spaced apart in a second direction. The first gate structure extends in the second direction on the first and second active patterns. The first channels are spaced apart in a third direction on the first active pattern. The second channels are spaced apart in the third direction on the second active pattern. The first source/drain layer having a first conductivity type is formed at a side of the first gate structure to contact the first channels. The second source/drain layer having a second conductivity type is formed at a side of the first gate structure to contact the second channels. Widths in the second direction of the first and second channels are different.

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