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公开(公告)号：US11770938B2
公开(公告)日：2023-09-26
申请号：US17592087
申请日：2022-02-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
CPC classification number: H10B63/24 , H10B63/84 , H10B63/845 , H10N70/063 , H10N70/231 , H10N70/826 , H10N70/828 , H10N70/8828
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US09780144B2
公开(公告)日：2017-10-03
申请号：US15342497
申请日：2016-11-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
IPC: H01L27/24
CPC classification number: H01L27/2427 , H01L27/2481 , H01L27/249 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144 , H01L45/1675
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US11227991B2
公开(公告)日：2022-01-18
申请号：US16916227
申请日：2020-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Sung-Ho Eun , Soon-Oh Park
Abstract: A semiconductor memory device includes first conductive lines extending in a first direction on a substrate, second conductive lines extending in a second direction over the first conductive line, the first and the second conductive lines crossing each other at cross points, a cell structure positioned at each of the cross points, each of the cell structures having a data storage element, a selection element to apply a cell selection signal to the data storage element and to change a data state of the data storage element, and an electrode element having at least an electrode with a contact area smaller than that of the selection element, and an insulation pattern insulating the first and the second conductive lines and the cell structures from one another.
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公开(公告)号：US10468594B2
公开(公告)日：2019-11-05
申请号：US15358544
申请日：2016-11-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Woo Lee , Soon-Oh Park , Jeong-Hee Park , Hideki Horii
Abstract: A variable resistance memory device includes a pattern of one or more first conductive lines, a pattern of one or more second conductive lines, and a memory structure between the first and second conductive lines. The pattern of first conductive lines extends in a first direction on a substrate, and the first conductive lines extend in a second direction crossing the first direction. The pattern of second conductive lines extends in the second direction on the first conductive lines, and the second conductive lines extend in the first direction. The memory structure vertically overlaps a first conductive line and a second conductive line. The memory structure includes an electrode structure, an insulation pattern on a central upper surface of the electrode structure, and a variable resistance pattern on an edge upper surface of the electrode structure. The variable resistance pattern at least partially covers a sidewall of the insulation pattern.
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公开(公告)号：US10374008B2
公开(公告)日：2019-08-06
申请号：US15655118
申请日：2017-07-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
IPC: H01L27/24
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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Patent Agency Ranking
公开(公告)号：US11587977B2
公开(公告)日：2023-02-21
申请号：US17173865
申请日：2021-02-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US10957740B2
公开(公告)日：2021-03-23
申请号：US16447370
申请日：2019-06-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Jun Seong , Soon-Oh Park
Abstract: A method of manufacturing a memory device includes sequentially forming and then etching a preliminary selection device layer, a preliminary middle electrode layer, and a preliminary variable resistance layer on a substrate, thereby forming a selection device, a middle electrode, and a variable resistance layer. At least one of a side portion of the selection device or a side portion of the variable resistance layer is removed so that a first width of the middle electrode in a first direction parallel to a top of the substrate is greater than a second width of the variable resistance layer in the first direction or a third width of the selection device in the first direction. A capping layer is formed on at least one of a side wall of the etched side portion of the selection device or a side wall of the etched side portion of the variable resistance layer.
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公开(公告)号：US10249816B2
公开(公告)日：2019-04-02
申请号：US15996605
申请日：2018-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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公开(公告)号：US10388867B2
公开(公告)日：2019-08-20
申请号：US15294873
申请日：2016-10-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Zhe Wu , Soon-Oh Park , Jeong-Hee Park , Dong-Ho Ahn , Hideki Horii
Abstract: A variable resistance memory device including a selection pattern; an intermediate electrode contacting a first surface of the selection pattern; a variable resistance pattern on an opposite side of the intermediate electrode relative to the selection pattern; and a first electrode contacting a second surface of the selection pattern and including a n-type semiconductor material, the second surface of the selection pattern being opposite the first surface thereof.
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公开(公告)号：US10026890B2
公开(公告)日：2018-07-17
申请号：US15177597
申请日：2016-06-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Uk Kim , Jung-Moo Lee , Soon-Oh Park , Jung-Hwan Park , Sug-Woo Jung
Abstract: A method of manufacturing a magnetoresistive random access memory device, the method including forming a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked; forming a first capping layer to cover a surface of the memory structure by a deposition process using a plasma under first conditions; and forming a second capping layer on the first capping layer by a deposition process using a plasma under second conditions different from the first conditions.
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