公开(公告)号：USRE50133E1

公开(公告)日：2024-09-17

申请号：US17506796

申请日：2021-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Artur Antonyan

IPC: G11C16/04 ,  G11C11/15 ,  G11C11/16 ,  G11C16/08 ,  G11C16/10 ,  H10B41/30 ,  H10B41/40

CPC classification number: G11C16/0433 ,  G11C11/15 ,  G11C11/1673 ,  G11C16/08 ,  G11C16/10 ,  H10B41/30 ,  H10B41/40

Abstract: A resistive memory device includes a plurality of word lines, a plurality of reference cells, a plurality of first resistive memory cells, a plurality of second resistive memory cells maintained in an off state, a read circuit configured to provide a first read current to the first resistive memory cells and provide a second read current to the reference cells while one of the first resistive memory cells is selected to perform a read operation, and a compensation circuit configured to provide a compensation current based on a first leakage current from the off resistive memory cells to the reference cells to compensate for a second leakage current generated by the unselected first resistive memory cells. Each reference cell is connected to one of the word lines and each of the first resistive memory cells are connected to one of the word lines.

公开(公告)号：US10910030B2

公开(公告)日：2021-02-02

申请号：US16390170

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Hyuntaek Jung ,  Suk-Soo Pyo

IPC: G11C11/16

Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.

公开(公告)号：US10896709B2

公开(公告)日：2021-01-19

申请号：US16688481

申请日：2019-11-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan

IPC: G11C11/16

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

公开(公告)号：US20190287603A1

公开(公告)日：2019-09-19

申请号：US16282930

申请日：2019-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Hyun-taek Jung

IPC: G11C11/4091 ,  G11C7/08 ,  G11C7/10

Abstract: Provided is a control signal generator for a sense amplifier, the control signal generator including a replica circuit including replica transistors corresponding to transistors included in the sense amplifier, and configured to receive at least one input signal of the sense amplifier and a first control signal for enabling a sensing operation by the sense amplifier; and an amplifying circuit configured to output, by amplifying an output signal from the replica circuit, a second control signal for enabling an amplifying operation by the sense amplifier after the sensing operation is enabled.

公开(公告)号：US20180374515A1

公开(公告)日：2018-12-27

申请号：US15989340

申请日：2018-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan

IPC: G11C5/14 ,  G11C11/16 ,  G11C8/10 ,  G11C8/08 ,  G11C16/30

CPC classification number: G11C5/145 ,  G11C5/147 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C16/30 ,  G11C29/021 ,  G11C29/028

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected to the memory cell array through word lines, a column decoder that is connected to the memory cell array through bit lines and source lines, a write driver that transfers a write voltage to a bit line, which is selected by the column decoder, from among the bit lines by using a gate voltage in a write operation, and control logic that generates the gate voltage. The gate voltage is higher than the write voltage.

公开(公告)号：US11217305B2

公开(公告)日：2022-01-04

申请号：US17007594

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Artur Antonyan

IPC: G11C11/00 ,  G11C16/04 ,  G11C13/00

Abstract: A nonvolatile memory device includes; a memory cell array including memory cells connected with bit lines and feedback cells connected with feedback bit lines, a row decoder connected with the memory cells and the feedback cells through word lines, a column decoder connected with the memory cells through the bit lines and connected with the feedback cells through the feedback bit lines, and a charge pump that generates a pump voltage provided to a selected word line among the word lines, wherein the charge pump is controlled in response to feedback currents flowing through the feedback bit lines.

公开(公告)号：US20210383844A1

公开(公告)日：2021-12-09

申请号：US17120405

申请日：2020-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Artur Antonyan

IPC: G11C7/04 ,  G11C11/16

Abstract: A memory device includes a cell array including a memory cell that includes a variable resistance element, a reference resistor configured to provide a resistance varying according to an adjustment code, and a read circuit configured to read data that is stored in the memory cell, based on a resistance of the variable resistance element and the resistance of the reference resistor. The memory device further includes a reference adjustment circuit configured to obtain a first calibration code corresponding to a temperature variation, and a second calibration code corresponding to a process variation, and perform an arithmetic operation on the obtained first calibration code and the obtained second calibration code, to obtain the adjustment code.

公开(公告)号：US10535392B2

公开(公告)日：2020-01-14

申请号：US16014011

申请日：2018-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan

IPC: G11C11/16

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

公开(公告)号：US10008249B2

公开(公告)日：2018-06-26

申请号：US15405336

申请日：2017-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Artur Antonyan

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1655 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

Abstract: A semiconductor memory device includes a memory cell array comprising a plurality of spin torque transfer-magnetic random access memory (STT-MRAM) cells connected to a plurality of word lines, a plurality of bit lines and a plurality of sense lines. A peripheral circuitry supplies cell current to the memory cells during read/write operations, such that the cell current supplied to memory cells of a selected word line vary according to a position of a word line group including the selected word line.

公开(公告)号：US12237005B2

公开(公告)日：2025-02-25

申请号：US18059574

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Ji Eun Kim

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096

Abstract: A nonvolatile memory device includes a memory cell array having nonvolatile memory cells therein, which are electrically connected to a plurality of word lines and a plurality of bit lines. A write driver and row decoder are provided, which are electrically connected to the plurality of bit lines and the plurality of word lines, respectively. Control logic is configured to transfer a first voltage to the write driver and a second voltage to the row decoder. The control logic includes: (i) a normal standby mode circuit configured to operate in a normal standby mode, and (ii) a deep standby mode circuit configured to operate in a deep standby mode. To save power, the layout areas of a plurality of elements within the deep standby mode circuit are smaller than layout areas of elements within the normal standby mode circuit, so that current flowing within the deep standby mode circuit during the deep standby mode is less than current flowing within the normal standby mode circuit during the normal standby mode.