公开(公告)号：US10510393B2

公开(公告)日：2019-12-17

申请号：US16118774

申请日：2018-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Suk-soo Pyo

IPC: G11C11/00 ,  G11C11/16 ,  G11C13/00 ,  H01L43/08 ,  G11C7/04 ,  G11C7/08

Abstract: Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.

公开(公告)号：US10762958B2

公开(公告)日：2020-09-01

申请号：US16127995

申请日：2018-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-soo Pyo ,  Hyun-taek Jung ,  So-hee Hwang ,  Tae-joong Song

IPC: G11C11/16 ,  G11C13/00 ,  G11C11/56

Abstract: A method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells is provided. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, monotonically increasing or monotonically decreasing reference currents. The method includes reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on an aggregation of results of the reading.

公开(公告)号：US10803971B2

公开(公告)日：2020-10-13

申请号：US16135325

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-soo Pyo ,  Hyun-taek Jung ,  Tae-joong Song

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/46 ,  G06F11/22 ,  G11C29/36 ,  G11C29/04

Abstract: A device for supporting a test mode for memory testing according to an example embodiment of the inventive concepts may include a memory configured to receive and store writing data and output reading data from the stored writing data; an error correction code (ECC) engine configured to generate the writing data by encoding input data and to generate output data by correcting error bits of N bits or less included in receiving data when N is a positive integer; and an error insertion circuit configured to provide the reading data to the ECC engine as the receiving data in a normal mode and to provide data obtained by inverting at least one bit of less than N bits of the reading data to the ECC engine as the receiving data in the test mode.