公开(公告)号：US09570411B2

公开(公告)日：2017-02-14

申请号：US14920927

申请日：2015-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gyu Baek ,  Young-Min Lee ,  Yun-Rae Cho ,  Sun-Dae Kim

IPC: H01L21/44 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

CPC classification number: H01L24/03 ,  H01L21/563 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/03614 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/08113 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/45099 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/181 ,  H01L2924/182 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A pad structure usable with a semiconductor device may include an insulating layer pattern structure, a plug, and a pad. The insulating layer pattern structure has a plug hole and at least one via hole. The plug is formed in the plug hole. The pad is formed on the insulating layer pattern structure. The pad is electrically connected with the plug and has a lower surface and an uneven upper surface. The lower surface includes a protruded portion inserted into the via hole. The uneven upper surface includes a recessed portion and an elevated portion—to provide high roughness and firm connection.

Abstract translation: 可用于半导体器件的焊盘结构可以包括绝缘层图案结构，插头和焊盘。 绝缘层图案结构具有插塞孔和至少一个通孔。 插头形成在插头孔中。 衬垫形成在绝缘层图案结构上。 垫与插头电连接，具有下表面和不平的上表面。 下表面包括插入通孔的突出部分。 不平坦的上表面包括凹部和升高部分，以提供高粗糙度和牢固的连接。

公开(公告)号：US09984945B2

公开(公告)日：2018-05-29

申请号：US15219457

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sun-Dae Kim ,  Nam-Gyu Baek ,  Hyung-Gil Baek

IPC: H01L21/66 ,  H01L21/67 ,  H01L23/58 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/2856 ,  G01R31/2884 ,  H01L21/67288 ,  H01L23/585

Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.

公开(公告)号：US20170062293A1

公开(公告)日：2017-03-02

申请号：US15219457

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun-Rae Cho ,  Sun-Dae Kim ,  Nam-Gyu Baek ,  Hyung-Gil Baek

IPC: H01L21/66 ,  G01R31/28 ,  H01L23/58

CPC classification number: H01L22/34 ,  G01R31/2856 ,  G01R31/2884 ,  H01L21/67288 ,  H01L23/585

Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line. Thus, although a crack may be generated in the corner of the semiconductor substrate by twice cutting processes of a wafer, the crack detection circuit may not detect the crack.

Abstract translation: 半导体芯片可以包括半导体衬底和裂纹检测电路。 半导体衬底可以包括电路结构。 裂纹检测电路可以包括主线和倒角线。 主线可以形成在半导体衬底中以包围电路结构。 倒角线可以形成在半导体衬底的角部。 倒角线可以连接在主线之间。 可以在每个倒角线和彼此垂直的两个主线中的任一个之间形成第一角度。 可以在每个倒角线和另一个主线之间形成比第一角宽的第二角度。 因此，尽管通过两次切割晶片的过程可能在半导体基板的拐角处产生裂纹，但是裂纹检测电路可能不会检测到裂纹。