NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT AND MEMORY SYSTEM HAVING THE SAME
    1.
    发明申请
    NONVOLATILE MEMORY DEVICE USING VARIABLE RESISTIVE ELEMENT AND MEMORY SYSTEM HAVING THE SAME 有权
    使用可变电阻元件的非易失性存储器件及其相关的存储器系统

    公开(公告)号:US20140198556A1

    公开(公告)日:2014-07-17

    申请号:US14099330

    申请日:2013-12-06

    Abstract: A nonvolatile memory device, which has an improved read reliability through a refresh operation, and a memory system, are provided. The nonvolatile memory device includes a resistive memory cell, a reference resistor corresponding to the resistive memory cell, a reference sense amplifier electrically connected to the reference resistor and configured to change a transition time of an output value of the reference resistor, and a refresh request signal generator configured to output the refresh request signal for the resistive memory cell when the transition time of an output value of the reference resistor is in a preset refresh requiring period.

    Abstract translation: 提供了通过刷新操作具有改善的读取可靠性的非易失性存储器件和存储器系统。 非易失性存储器件包括电阻存储单元,对应于电阻存储单元的参考电阻,与参考电阻器电连接并被配置为改变参考电阻器的输出值的转换时间的参考读出放大器和刷新请求 信号发生器被配置为当参考电阻器的输出值的转换时间处于预设的刷新需求周期时,输出用于电阻性存储器单元的刷新请求信号。

    RESISTIVE MEMORY DEVICE COMPRISING SELECTIVELY DISABLED WRITE DRIVER
    3.
    发明申请
    RESISTIVE MEMORY DEVICE COMPRISING SELECTIVELY DISABLED WRITE DRIVER 有权
    包含选择性禁止写入驱动器的电阻式存储器件

    公开(公告)号:US20140211538A1

    公开(公告)日:2014-07-31

    申请号:US13798374

    申请日:2013-03-13

    Abstract: A nonvolatile memory device comprises a resistive memory cell, a write driver configured to write data to the resistive memory cell during a write period comprising a plurality of loops, and a sense amplifier configured to verify whether the data is correctly written to the resistive memory cell in each of the loops. Where the sense amplifier verifies that the data is correctly written in a k-th loop among the loops, the write driver is disabled from a (k+1)-th loop to an end of the write period.

    Abstract translation: 非易失性存储器件包括电阻存储器单元,写入驱动器,配置为在包括多个环路的写入周期期间将数据写入电阻存储器单元;以及读出放大器,其被配置为验证数据是否被正确写入电阻存储器单元 在每个循环中。 在感测放大器验证数据在循环中的第k个循环中被正确地写入的情况下,写入驱动器被禁止从第(k + 1)个循环到写周期的结束。

    NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE
    5.
    发明申请
    NONVOLATILE MEMORY DEVICE USING RESISTANCE MATERIAL AND METHOD OF DRIVING THE NONVOLATILE MEMORY DEVICE 有权
    使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法

    公开(公告)号:US20140119094A1

    公开(公告)日:2014-05-01

    申请号:US13940856

    申请日:2013-07-12

    Abstract: Provided is a nonvolatile memory device using a resistance material and a method of driving the nonvolatile memory device. The nonvolatile memory device comprises a resistive memory cell which stores multiple bits; a sensing node; a clamping unit coupled between the resistive memory cell and the sensing node and provides a clamping bias to the resistive memory cell; a compensation unit which provides a compensation current to the sensing node; a sense amplifier coupled to the sensing node and senses a change in a level of the sensing node; and an encoder which codes an output value of the sense amplifier in response to a first clock signal. The clamping bias varies over time. The compensation current is constant during a read period.

    Abstract translation: 提供了使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法。 非易失性存储器件包括存储多个位的电阻存储器单元; 感测节点; 耦合在所述电阻存储器单元和所述感测节点之间的钳位单元,并向所述电阻性存储单元提供钳位偏置; 补偿单元,其向感测节点提供补偿电流; 感测放大器耦合到感测节点并感测感测节点的电平的变化; 以及编码器,其响应于第一时钟信号对读出放大器的输出值进行编码。 钳位偏置随时间而变化。 补偿电流在读取期间是恒定的。

    Nonvolatile memory device using resistance material and method of driving the nonvolatile memory device
    6.
    发明授权
    Nonvolatile memory device using resistance material and method of driving the nonvolatile memory device 有权
    使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法

    公开(公告)号:US09082478B2

    公开(公告)日:2015-07-14

    申请号:US13940856

    申请日:2013-07-12

    Abstract: Provided is a nonvolatile memory device using a resistance material and a method of driving the nonvolatile memory device. The nonvolatile memory device comprises a resistive memory cell which stores multiple bits; a sensing node; a clamping unit coupled between the resistive memory cell and the sensing node and provides a clamping bias to the resistive memory cell; a compensation unit which provides a compensation current to the sensing node; a sense amplifier coupled to the sensing node and senses a change in a level of the sensing node; and an encoder which codes an output value of the sense amplifier in response to a first clock signal. The clamping bias varies over time. The compensation current is constant during a read period.

    Abstract translation: 提供了使用电阻材料的非易失性存储器件和驱动非易失性存储器件的方法。 非易失性存储器件包括存储多个位的电阻存储器单元; 感测节点; 耦合在所述电阻存储器单元和所述感测节点之间的钳位单元,并向所述电阻性存储单元提供钳位偏置; 补偿单元,其向感测节点提供补偿电流; 感测放大器耦合到感测节点并感测感测节点的电平的变化; 以及编码器,其响应于第一时钟信号对读出放大器的输出值进行编码。 钳位偏置随时间而变化。 补偿电流在读取期间是恒定的。

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