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公开(公告)号：US20210405967A1
公开(公告)日：2021-12-30
申请号：US17093889
申请日：2020-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul Jung , Sungmeen Myung , Sangjoon Kim
Abstract: A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.
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公开(公告)号：US11989531B2
公开(公告)日：2024-05-21
申请号：US17473139
申请日：2021-09-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen Myung , Seungchul Jung , Sangjoon Kim
Abstract: A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.
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公开(公告)号：US12141687B2
公开(公告)日：2024-11-12
申请号：US17195917
申请日：2021-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul Jung , Sangjoon Kim , Sungmeen Myung
IPC: G06N3/065 , G06F7/544 , G11C11/4094 , H10B61/00 , G06N3/048
Abstract: A processing device includes: a plurality of bitcells, each of the plurality of bitcells including: a variable resistor layer including a plurality of active variable resistors and a plurality of inactive variable resistors; an active layer including a plurality of switches configured to control either one of a voltage to be applied between ends of each of the active variable resistors and a current flowing to each of the active variable resistors; and a plurality of metal layers including wires electrically connecting the active variable resistors to the switches, wherein at least one of the plurality of bitcells includes a via penetrating through the variable resistor layer and connecting at least one of the switches to at least one of the active variable resistors.
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Patent Agency Ranking
公开(公告)号：US11816447B2
公开(公告)日：2023-11-14
申请号：US17093889
申请日：2020-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seungchul Jung , Sungmeen Myung , Sangjoon Kim
CPC classification number: G06F7/5443 , G01R19/16538 , G01R27/02 , G04F10/005 , G06N3/08 , H03K5/24
Abstract: A method of performing a predetermined operation for a circuit that includes a resistor group, one end of the resistor group being configured for connection to a power supply unit, the other end of the resistor group being configured for connection to a sampling capacitor, and a parasitic capacitance existing at each node between resistors of the resistor group. The method includes in a forward process, determining a time when a sampling capacitor voltage applied to the sampling capacitor reaches a first reference voltage as a switching time; at the switching time, connecting the sampling capacitor to a ground or predetermined voltage and floating the power supply unit; in a backward process, after the switching time, determining a time when a power supply unit voltage applied to the power supply unit reaches a second reference voltage as an end time; and performing the predetermined operation based on the end time.
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公开(公告)号：US12050886B2
公开(公告)日：2024-07-30
申请号：US17075774
申请日：2020-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen Myung , Sangjoon Kim , Seungchul Jung
CPC classification number: G06F7/5443 , G01R19/0046 , G06F13/4022 , G06F13/4282 , G06N3/04 , G11C11/161 , G11C11/1673 , G11C11/54
Abstract: A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.
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公开(公告)号：US20210303266A1
公开(公告)日：2021-09-30
申请号：US17075774
申请日：2020-10-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sungmeen Myung , Sangjoon Kim , Seungchul Jung
Abstract: A neuromorphic device includes a first resistor line having a plurality of first resistors that are serially connected to each other, a second resistor line having a plurality of second resistors that are serially connected to each other, one or more current sources to control a current flowing in each of the first resistor line and the second resistor line to a respective current value, a first capacitor electrically connectable to the first resistor line, and a second capacitor electrically connectable to the second resistor line.
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公开(公告)号：US12198775B2
公开(公告)日：2025-01-14
申请号：US18091258
申请日：2022-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungmeen Myung , Seok Ju Yun , Jaehyuk Lee , Seungchul Jung
Abstract: A method and memory device with in-memory computing defection detection is disclosed. A memory device includes a memory including banks, wherein each bank includes a respective plurality of bit-cells, an in-memory computation (IMC) operator configured to perform an IMC operation between first data while the first data is in the bit-cells of the memory and second data received as input to the memory device, wherein the banks share the operator, and wherein the memory device is configured to: generate a first test pattern that is stored in the memory and generate a second test pattern applied to the IMC operator, and based thereon determine whether a defect has occurred in either the memory or the operator, and perform a repair based on the determination that a defect has occurred.
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公开(公告)号：US12197891B2
公开(公告)日：2025-01-14
申请号：US17702170
申请日：2022-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungchul Jung , Sang Joon Kim , Sungmeen Myung , Seok Ju Yun , Seungkeun Yoon
Abstract: A computing device for performing a digital pulse-based crossbar operation and a method of operating the computing device. The computing device includes a plurality of input lines to which a pulse is selectively input in a sequential manner based on a corresponding input signal; a plurality of output lines crossing the input lines; a plurality of elements, each element being disposed at a cross point between a corresponding input line and a corresponding output line to transfer, to the corresponding output line, a pulse input to the corresponding input line in response to a corresponding weight being a first value; and a plurality of pulse counters, each pulse counter counting a number of pulses output from a corresponding output line.
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