公开(公告)号：US10983584B2

公开(公告)日：2021-04-20

申请号：US16439159

申请日：2019-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Soo Choi ,  Hyun Jin Choi ,  Jinwoo Kim ,  Yu-Hun Jun

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3246 ,  G11C7/00

Abstract: An operation method of an electronic device including a core includes reading first status information from a first status register of a first functional block driven independently of the core, reading second status information from a second status register of a second functional block driven independently of the core, reading first change information from a first flag register of the first functional block, reading second change information from a second flag register of the second functional block, determining whether an operation status of the electronic device is any one status of an idle status and a busy status, based on the read first and second status information and the read first and second change information, and operating in an operation mode corresponding to the determined operation status.

公开(公告)号：US09772940B2

公开(公告)日：2017-09-26

申请号：US14579179

申请日：2014-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Soo Choi ,  Eun-Ju Park

IPC: G06F12/02

CPC classification number: G06F12/0253 ,  G06F12/0246 ,  G06F2212/7202

Abstract: A method of operating a storage device comprises copying first valid pages in a first block into a first latch unit based on a first volatile memory device, the first block being set on multiple nonvolatile memory devices, copying second valid pages in the first block into a second latch unit based on the first volatile memory device, and copying the first valid pages in the first latch unit and the second valid pages in the second latch unit into a second block, the second block being set on the nonvolatile memory devices and being different from the first block.

公开(公告)号：US20210157528A1

公开(公告)日：2021-05-27

申请号：US17167772

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Wan-Soo Choi

IPC: G06F3/06

Abstract: A method of operating a multi-bank storage device includes transmitting a write command including stream identification information to the multi-bank storage device, and allocating at least one bank, in which data associated with the write command is to be stored, from among a plurality of banks in the multi-bank storage device, based on striping size information included within the stream identification information. Upon allocation, the data is written into the allocated at least one bank.

公开(公告)号：US20200150899A1

公开(公告)日：2020-05-14

申请号：US16413755

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Wan-Soo Choi

IPC: G06F3/06

Abstract: An operating method of a storage device which includes a plurality of banks includes receiving a write command including stream identification information from a host, allocating a bank, in which data are to be stored, from among the plurality of banks based on a striping size corresponding to the stream identification information, in response to the write command, and writing the data in the allocated bank.

公开(公告)号：US11989451B2

公开(公告)日：2024-05-21

申请号：US17494007

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Hyun Seon Park

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A method for operating a memory controller, the method including: receiving a first command from a first host; storing the first command in a queue; when the first command has a higher priority than a second command currently being performed, pausing an operation of the second command and performing a read operation of the first command; and continuing the operation of the second command after completion of the read operation of the first command.

公开(公告)号：US20220206714A1

公开(公告)日：2022-06-30

申请号：US17477865

申请日：2021-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Do Hyeon Park

IPC: G06F3/06

Abstract: A method of operating a storage device including a non-volatile memory and a multi-core processor with at least two cores includes the following steps: receiving, by a host interface of the storage device, a first command from a host for requesting the non-volatile memory to perform a predetermined memory operation; generating, by a task scheduler of the storage device, first and second tasks from the first memory command; selecting, by the task scheduler, a first core from among the at least two cores based on execution times of the at least two cores; assigning, by the task scheduler, the first and second tasks to the first core; and requesting, by the first core, a subsequent task from the scheduler while the first core processes the first assigned task and loads code for processing the second task.

公开(公告)号：US10942679B2

公开(公告)日：2021-03-09

申请号：US16413755

申请日：2019-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Wan-Soo Choi

IPC: G06F3/06

Abstract: An operating method of a storage device which includes a plurality of banks includes receiving a write command including stream identification information from a host, allocating a bank, in which data are to be stored, from among the plurality of banks based on a striping size corresponding to the stream identification information, in response to the write command, and writing the data in the allocated bank.

公开(公告)号：US12019918B2

公开(公告)日：2024-06-25

申请号：US17883261

申请日：2022-08-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Soo Choi ,  Young Wook Kim ,  Dong Eun Shin ,  Yong Chan Jo

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/0661 ,  G06F3/0673 ,  G06F9/485 ,  G06F9/546

Abstract: A storage device includes an input stage receiving a first command, a queue manager allocating a first queue entry for the first command, a pre-processor storing the first command in the first queue entry and updating a task list with the first command and a core executing the first command in accordance with an order specified in the updated task list. At least one of the queue manager and the pre-processor is implemented in a customized logic circuit.

公开(公告)号：US10564869B2

公开(公告)日：2020-02-18

申请号：US16057849

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Young-Wook Kim ,  Wan-Soo Choi

IPC: G06F3/06

Abstract: A method of controlling memory devices of a memory controller, the memory devices including a plurality of memory dies, includes receiving at least one data operation request and a power budget from external of the memory controller; determining respective data operation times of the plurality of memory dies, wherein a power consumption due to at least one data operation in response to the at least one data operation request may be equal to or less than the power budget; and controlling the plurality of memory dies based on the data operation times.

公开(公告)号：US09147475B2

公开(公告)日：2015-09-29

申请号：US13945460

申请日：2013-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Woo Jung ,  Heetak Shin ,  Jinwoo Jung ,  Wan-Soo Choi

IPC: G11C11/56 ,  G11C16/10

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/32 ,  G11C2211/5622 ,  G11C2211/5641

Abstract: A storage device is provided which includes a plurality of memory chips each nonvolatile memory cells divided into a first memory region and a second memory region; and a memory controller configured to buffer data provided from the exterior and to control the plurality of memory chips to perform a buffer-program operation and a main-program operation. The buffered data is stored at the first memory region at the buffer-program operation and data stored at the first memory region is written at the second memory region at the main-program operation. During a main-program operation of a first memory chip among the plurality of memory chips, the memory controller buffers data to be written at a second memory chip.

Abstract translation: 提供存储装置，其包括多个存储器芯片，每个非易失性存储器单元分成第一存储区域和第二存储器区域; 以及存储器控制器，被配置为缓冲从外部提供的数据并且控制所述多个存储器芯片以执行缓冲器程序操作和主程序操作。 缓冲数据以缓冲器程序操作存储在第一存储器区域，并且存储在第一存储器区域的数据被写入主程序操作的第二存储器区域。 在多个存储器芯片中的第一存储器芯片的主程序操作期间，存储器控制器缓冲要写入第二存储器芯片的数据。