公开(公告)号：US20240090220A1

公开(公告)日：2024-03-14

申请号：US18367619

申请日：2023-09-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin JUNG ,  Byongju KIM ,  Wonjun PARK ,  Donghwa LEE ,  Changheon CHEON ,  Dongsung CHOI

IPC: H10B43/27 ,  G11C5/06 ,  G11C16/04 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C16/0483 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor device includes a plurality of gate electrodes spaced apart from each other in a vertical direction on a substrate, a plurality of channel structures respectively penetrating a plurality of gate electrodes and extending in the vertical direction, each comprising a channel layer having a stacked structure of a first oxide semiconductor channel layer and a second oxide semiconductor channel layer which have different conductivities, and a gate insulating layer disposed between the channel layer and each of the plurality of gate electrodes, and a plurality of bit lines disposed on the plurality of channel structures and respectively connected to the plurality of channel structures, and the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed.

公开(公告)号：US20220085286A1

公开(公告)日：2022-03-17

申请号：US17384933

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonghee PARK ,  Dongho AHN ,  Wonjun PARK

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor device includes a first conductive line on a lower structure and extending in a first horizontal direction; a second conductive line on the first conductive line and extending in a second horizontal direction, the second horizontal direction being perpendicular to the first horizontal direction; and a memory cell structure between the first conductive line and the second conductive line. The memory cell may structure include a data storage material pattern and a selector material pattern overlapping the data storage material pattern in a vertical direction. The data storage material pattern may include a phase change material layer of InαGeβSbγTeδ. In the phase change material layer of InαGeβSbγTeδ, a sum of α and β may be lower than about 30 at. %, and a sum of γ and δ may be higher than about 70 at. %.

公开(公告)号：US20240244846A1

公开(公告)日：2024-07-18

申请号：US18236637

申请日：2023-08-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjun PARK ,  Byongju KIM ,  Jaemin JUNG ,  Kwangmin PARK ,  Donghwa LEE ,  Dongsung CHOI

IPC: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

CPC classification number: H10B43/35 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device includes a substrate; a stack structure including an interlayer insulating layer and a gate electrode which are alternately stacked on the substrate; a channel layer extending in a direction crossing the substrate through the stack structure; and a gate dielectric layer between the gate electrode and the channel layer, the gate dielectric layer including a tunneling layer, a charge storage layer, and a blocking layer sequentially on the channel layer, wherein the tunneling layer includes a carbon-containing layer including carbon, and the tunneling layer is positioned closer to the channel layer than it is to the charge storage layer.

公开(公告)号：US20240081075A1

公开(公告)日：2024-03-07

申请号：US18131924

申请日：2023-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byongju KIM ,  Dongsung CHOI ,  Wonjun PARK ,  Donghwa LEE ,  Jaemin JUNG ,  Changheon CHEON

IPC: H10B43/40 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

CPC classification number: H10B43/40 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.

公开(公告)号：US20240196618A1

公开(公告)日：2024-06-13

申请号：US18528970

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byongju KIM ,  Dongsung CHOI ,  Wonjun PARK ,  Donghwa LEE ,  Jaemin JUNG ,  Changheon CHEON

IPC: H10B43/27 ,  H10B41/27 ,  H10B51/20

CPC classification number: H10B43/27 ,  H10B41/27 ,  H10B51/20 ,  G11C16/14

Abstract: An integrated circuit device includes a semiconductor substrate; a plurality of conductive lines extending on the semiconductor substrate in a horizontal direction and overlapping each other in a vertical direction; a plurality of insulating layers between pairs of conductive lines of the plurality of conductive lines and extending in the horizontal direction; and a channel structure passing through the plurality of conductive lines and the plurality of insulating layers, wherein the channel structure includes a core insulating layer, a channel layer on a side wall and a bottom surface of the core insulating layer, a gate insulating layer on an outer wall of the channel layer, and a ferroelectric layer on an outer wall of the gate insulating layer.

公开(公告)号：US20230301218A1

公开(公告)日：2023-09-21

申请号：US18119970

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjun PARK ,  Chungman KIM ,  Dongho AHN ,  Changyup PARK

IPC: H10N70/00 ,  H10N70/20 ,  H10B63/00

CPC classification number: H10N70/8828 ,  H10B63/80 ,  H10N70/063 ,  H10N70/231 ,  H10N70/841

Abstract: A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CaGedSbcTedAeXf, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.