公开(公告)号：US10141427B2

公开(公告)日：2018-11-27

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom Kim ,  Hong-Sik Yoon ,  Bon-Young Koo ,  Wook-Je Kim

IPC: H01L29/66 ,  H01L29/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

公开(公告)号：US20160149003A1

公开(公告)日：2016-05-26

申请号：US14855533

申请日：2015-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Wook-Je Kim ,  Baek-Hap Choi ,  Jin-Hee Han ,  Hyun-Gi Hong

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8258 ,  H01L29/6659 ,  H01L29/7834

Abstract: In methods of manufacturing a semiconductor device, a stress channel layer is formed on a semiconductor substrate. A first ion-implantation process is performed on the semiconductor substrate or the stress channel layer at a temperature ranging from about 100° C. to about 600° C. A gate structure is formed on the stress channel layer. A first source/drain region is formed at an upper portion of the stress channel layer adjacent to the gate structure.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底上形成应力沟道层。 在约100℃至约600℃的温度范围内，在半导体衬底或应力沟道层上进行第一离子注入工艺。在应力沟道层上形成栅极结构。 第一源极/漏极区域形成在与栅极结构相邻的应力沟道层的上部。

公开(公告)号：US09299811B2

公开(公告)日：2016-03-29

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。

公开(公告)号：US20150147860A1

公开(公告)日：2015-05-28

申请号：US14519771

申请日：2014-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wook-Je Kim ,  Jae-Yup Chung ,  Jong-Seo Hong ,  Cheol Kim ,  Hee-Soo Kang ,  Hyun-Jo Kim ,  Hee-Don Jeong ,  Soo-Hun Hong ,  Sang-Bom Kang ,  Myeong-Cheol Kim ,  Young-Su Chung

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.

Abstract translation: 半导体器件可以包括从基板突出的第一和第二鳍片，沿第一方向延伸，并且在第一方向上彼此分离。 半导体器件还可以包括场绝缘层，其设置在第一和第二鳍之间，沿与第一方向相交的第二方向延伸，形成在场绝缘层上的蚀刻停止层图案和伪栅极结构， 形成在蚀刻停止层图案上。