公开(公告)号：US10593557B2

公开(公告)日：2020-03-17

申请号：US16123262

申请日：2018-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung-In Choi ,  Sang-Hoon Han ,  Sun-Jung Kim ,  Tae-Gon Kim ,  Hyun-Chul Song

IPC: H01L21/4763 ,  H01L21/3115 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/8234 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device, the method including forming dummy gate structures on a substrate; forming spacers on sidewalls of the dummy gate structures; forming a preliminary first interlayer insulation pattern to fill a gap between adjacent spacers; etching an upper portion of the preliminary first interlayer insulation pattern through a first etching process to form a preliminary second interlayer insulation pattern; implanting an ion on the dummy gate structures, the spacers, and the preliminary second interlayer insulation pattern through an ion-implanting process; etching an upper portion of the preliminary second interlayer insulation pattern through a second etching process to form an interlayer insulation pattern having a flat upper surface; and forming a capping pattern on the interlayer insulation pattern to fill a gap between the spacers.

公开(公告)号：US20160300932A1

公开(公告)日：2016-10-13

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom KIM ,  Hong-Sik YOON ,  Bon-Young KOO ,  Wook-Je KIM

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66545 ,  H01L29/785 ,  H01L2924/13067

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

Abstract translation: 半导体器件包括衬底上的栅极图案，栅极图案下方的跨越栅极图案的多通道有源图案，并且具有不与栅极图案重叠的第一区域和与栅极图案重叠的第二区域， 多通道活性图案沿着第一区域的外周边并且包括具有浓度的杂质和多通道活性图案上的衬垫，衬垫在第一区域的侧表面上延伸并且不在第一区域的顶表面上延伸 第一个地区。 还描述了相关的制造方法。

公开(公告)号：US20160149003A1

公开(公告)日：2016-05-26

申请号：US14855533

申请日：2015-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Wook-Je Kim ,  Baek-Hap Choi ,  Jin-Hee Han ,  Hyun-Gi Hong

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8258 ,  H01L29/6659 ,  H01L29/7834

Abstract: In methods of manufacturing a semiconductor device, a stress channel layer is formed on a semiconductor substrate. A first ion-implantation process is performed on the semiconductor substrate or the stress channel layer at a temperature ranging from about 100° C. to about 600° C. A gate structure is formed on the stress channel layer. A first source/drain region is formed at an upper portion of the stress channel layer adjacent to the gate structure.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底上形成应力沟道层。 在约100℃至约600℃的温度范围内，在半导体衬底或应力沟道层上进行第一离子注入工艺。在应力沟道层上形成栅极结构。 第一源极/漏极区域形成在与栅极结构相邻的应力沟道层的上部。

公开(公告)号：US10141427B2

公开(公告)日：2018-11-27

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom Kim ,  Hong-Sik Yoon ,  Bon-Young Koo ,  Wook-Je Kim

IPC: H01L29/66 ,  H01L29/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

公开(公告)号：US09812559B2

公开(公告)日：2017-11-07

申请号：US15236726

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Bong-Soo Kim ,  Hyun-Seung Kim ,  Hyun-Gi Hong

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.