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公开(公告)号：US20240290401A1
公开(公告)日：2024-08-29
申请号：US18385185
申请日：2023-10-30
发明人： Yohan LEE , Jaeduk YU , Sangsoo PARK , Yonghyuk CHOI
CPC分类号： G11C16/345 , G11C16/0433 , G11C16/08
摘要： A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.
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公开(公告)号：US20220150619A1
公开(公告)日：2022-05-12
申请号：US17519753
申请日：2021-11-05
发明人： Choonghyo PARK , Kiwon KIM , Myoungsung SIM , Changshik YOON , Woojin CHO , Joonrae CHO , Hyunggwang KANG , Byounghee LEE , Sangsoo PARK , Hochul HWANG
摘要： According to various embodiments of the disclosure, an electronic device may include: a first housing, a second housing accommodating at least a portion of the first housing and configured to guide sliding movement of the first housing, a flexible display including a first display area disposed on the first housing and a second display area extending from the first display area, a speaker module including a speaker unit including at least one speaker disposed in the second housing and a speaker enclosure accommodating the speaker unit and including a vent hole, and a seal connected to the first housing and the speaker enclosure and configured to be variable based on the sliding movement of the first housing.
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公开(公告)号：US20240282383A1
公开(公告)日：2024-08-22
申请号：US18409344
申请日：2024-01-10
发明人： Yohan LEE , Jaeduk YU , Sangsoo PARK
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/10 , G11C16/26
摘要： A memory device including: a memory cell array including a plurality of memory blocks; a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block of the plurality of memory blocks on which an erase operation is to be performed; and a control logic circuit configured to control the memory cell array and the voltage generator, wherein, during the erase operation, after a precharge voltage is applied to a plurality of string select lines connected to the target block, the control logic circuit is further configured to provide the erase voltage to a plurality of bit lines connected to the plurality of string select lines, wherein the plurality of string select lines includes a first string select line and a second string select line, wherein a first distance between the first string select line and ends of a plurality of word lines connected to the target block is less than a second distance between the second string select line and the ends of the plurality of word lines, and wherein a first threshold voltage of a first transistor connected to the first string select line is higher than a second threshold voltage of a second transistor connected to the second string select line.
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公开(公告)号：US20240274206A1
公开(公告)日：2024-08-15
申请号：US18385073
申请日：2023-10-30
发明人： Yongseok KWON , Jaeduk YU , Sangsoo PARK , Jonghoon PARK , Jauang YOON
摘要： The present disclosure provides nonvolatile memory devices including high-voltage switch circuits and methods of controlling the same. In some embodiments, a nonvolatile memory device includes a voltage generator configured to generate a switching source voltage, a plurality of high-voltage switch circuits grouped into a plurality of switching groups and configured to generate a plurality of switch control signals based on the switching source voltage, a conductive path configured to transfer the switching source voltage from the voltage generator to the plurality of high-voltage switch circuits, a plurality of high-voltage switches configured to transfer high voltages based on the plurality of switch control signals, and a control circuit configured to control transition timing of the plurality of switch control signals independently with respect to each of the plurality of switching groups.
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公开(公告)号：US20170242652A1
公开(公告)日：2017-08-24
申请号：US15436241
申请日：2017-02-17
发明人： Sangsoo PARK , Jaehyun KIM , Limsam LIM , Namil LEE , Hochul HWANG
CPC分类号： G06F3/165 , G11B20/10527 , G11B2020/10888 , H04R3/00 , H04R3/04 , H04R2420/07 , H04R2430/01
摘要： Methods and apparatuses are provided for processing audio data at an electronic device. Audio data is obtained. A type of the audio data is identified. An audio processing mode corresponding to the type of the audio data is selected. An audio track of the audio data is output, based on the audio processing mode.
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公开(公告)号：US20220295178A1
公开(公告)日：2022-09-15
申请号：US17568171
申请日：2022-01-04
发明人： Myeongwan GANG , Jaehyun KIM , Sangsoo PARK , Hakhoon SONG , Dongmoon OK , Byeongjun KIM , Kyoungho BANG
摘要： An electronic device and method are disclosed. The electronic device includes an internal microphone, a communication module, and at least one processor. The processor implements the method, including: receiving, through the communication module, a first audio signal input through an external microphone included in an external electronic device communicatively connected to the electronic device, activating the internal microphone in response to detecting a device switch event switching from the external microphone to the internal microphone while receiving the first audio signal, receiving a second audio signal input through the internal microphone, synchronizing and mixing the first audio signal and the second audio signal during a designated first time period, and deactivating the external microphone upon detecting lapse of the designated first time period.
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公开(公告)号：US20240221844A1
公开(公告)日：2024-07-04
申请号：US18532730
申请日：2023-12-07
发明人： Jaeduk YU , Jonghoon PARK , Yohan LEE , Sangsoo PARK
CPC分类号： G11C16/26 , G11C16/0433 , G11C16/08
摘要： Provided is an operating method of a nonvolatile memory device. The operating method includes receiving a read command, increasing a voltage applied to a plurality of unselected ground selection lines from an off voltage to an on voltage during a word line setup period, applying a first voltage to a first selected ground selection line corresponding to a first process characteristic, until a first time in the word line setup period, applying a second voltage to the first selected ground selection line after the first time in the word line setup period, applying the first voltage to a second selected ground selection line corresponding to a second process characteristic, until a second time earlier than the first time in the word line setup period, and applying the second voltage to the second selected ground selection line after the second time in the word line setup period.
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公开(公告)号：US20220036953A1
公开(公告)日：2022-02-03
申请号：US17221833
申请日：2021-04-04
发明人： Sungmin JOE , Sangsoo PARK , Joonsuc JANG , Kihoon KANG , Yonghyuk CHOI
摘要： A nonvolatile memory device that performs two-way channel precharge during programming is provided. A program operation of the nonvolatile memory device simultaneously performs a first precharge operation in a bit line direction and a second precharge operation in a source line direction on channels of a plurality of cell strings before programming a selected memory cell to initialize the channels. The first precharge operation precharges the channels of the plurality of cell strings using a first precharge voltage applied to the bit line through first and second string selection transistors, and the second precharge operation precharges the channels of the plurality of cell strings using a second precharge voltage applied to the source line through first and second ground selection transistors.
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公开(公告)号：US20210224028A1
公开(公告)日：2021-07-22
申请号：US17148694
申请日：2021-01-14
发明人： Hyunwook KIM , Sangsoo PARK , Hangil MOON , Hyunchul YANG , Sanghoon LEE , Kalicharan GAJULA
IPC分类号： G06F3/16
摘要： An audio output device according to an embodiment may include: a short-range communication module configured to perform short-range wireless communication; a memory configured to buffer audio data received from an external electronic device through the short-range communication module; an audio output unit configured to output the audio data; and a processor. The processor may be configured to: receive operation mode information related to a function being executed in the external electronic device from the external electronic device through the short-range communication module; configure a reference period corresponding to an amount of the audio data buffered in the memory based on the operation mode information; and determine a playback speed of the audio data to be output through the audio output unit by comparing the amount of the buffered audio data with the configured reference period. In addition, various other embodiments may be possible.
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公开(公告)号：US20210120339A1
公开(公告)日：2021-04-22
申请号：US17042429
申请日：2019-04-15
发明人： Beakkwon SON , Yangsu KIM , Sangsoo PARK , Jaeha PARK , Jaemo YANG , Keunwon JANG , Hyunmin CHOI , Gangyoul KIM , Hangil MOON
IPC分类号： H04R5/04
摘要： An electronic device, according to various embodiments of the present invention, comprises: a first speaker arranged on one side end of the electronic device; a second speaker arranged on the other side end of the electronic device; at least one sensor; and a processor, wherein the processor may be configured so as to receive a first audio signal, acquire a first channel signal and a second channel signal by using the first audio signal, acquire state information associated with the electronic device by using the at least one sensor, correct at least one portion of the first channel signal on the basis of at least the state information, output the corrected first channel signal using the first speaker, and output the second channel signal using the second speaker. In addition, various embodiments are possible.
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