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    Memory device and method for driving the same
    1.
    发明授权
    Memory device and method for driving the same 有权
    记忆装置及其驱动方法

    公开(公告)号：US09269412B2

    公开(公告)日：2016-02-23

    申请号：US14198028

    申请日：2014-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yong Shim ,  In-Dal Song ,  Young Choi

    IPC: G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

    CPC classification number: G11C7/1072 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

    Abstract: A memory device is provided. The memory device includes programming first bit data into a plurality of memory cells; identifying target memory cells which are in a first state and whose threshold voltages are equal to or greater than a first voltage from the memory cells programmed with the first bit data; receiving second bit data which is to be programmed into the memory cells; calculating a plurality of third bit data by performing a first process on the second bit data; selecting third bit data which changes a largest number of target memory cells from the first state to a second state in response to the memory cells being programmed with each of the plurality of third bit data from the plurality of third bit data; and programming the selected third bit data into the memory cells.

    Abstract translation: 提供存储器件。 存储器件包括将第一位数据编程到多个存储器单元中; 识别处于第一状态并且其阈值电压等于或大于来自用第一位数据编程的存储器单元的第一电压的目标存储器单元; 接收要编程到存储器单元中的第二位数据; 通过对所述第二位数据执行第一处理来计算多个第三位数据; 响应于来自多个第三位数据的多个第三位数据中的每一个对存储器单元进行编程，选择将最大数目的目标存储器单元从第一状态改变到第二状态的第三位数据; 并将所选择的第三位数据编程到存储器单元中。

    ANALOG-TO-DIGITAL CONVERSION
    2.
    发明申请
    ANALOG-TO-DIGITAL CONVERSION 有权

    公开(公告)号：US20250038754A1

    公开(公告)日：2025-01-30

    申请号：US18658820

    申请日：2024-05-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaeha Kim ,  Young Choi ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H03M1/06

    Abstract: The present disclosure relates to successive approximation register analog-to-digital converters. An example successive approximation register analog-to-digital converter includes a first sampling and holding circuit that samples an analog signal at a first point in time and generates a first input voltage, a second sampling and holding circuit that samples the analog signal at a second point in time and generates a second input voltage, and a first analog-to-digital converter. The first analog-to-digital converter performs a feed forward equalization function by receiving the first input voltage and the second input voltage, sampling the first input voltage and the second input voltage, and outputting a multi-bit digital signal based on a sampling result of the first input voltage and a sampling result of the second input voltage.

    RECEIVERS INCLUDING HIGH SPEED DECISION FEEDBACK EQUALIZERS, COMMUNICATION SYSTEMS AND OPERATING METHODS THEREOF
    4.
    发明申请
    RECEIVERS INCLUDING HIGH SPEED DECISION FEEDBACK EQUALIZERS, COMMUNICATION SYSTEMS AND OPERATING METHODS THEREOF 有权

    公开(公告)号：US20240406041A1

    公开(公告)日：2024-12-05

    申请号：US18422058

    申请日：2024-01-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Young Choi ,  Jaeha Kim ,  Meyong Su Ko ,  Myoungbo Kwak ,  Jaewoo Park ,  Youngdon Choi ,  Junghwan Choi

    IPC: H04L25/06 ,  H04L1/1867

    Abstract: A receiver for receiving a data signal, comprising, an analog-to-digital converter configured to convert the data signal into digital data, a first-in-first-out buffer configured to determine a frame boundary of the digital data by referring to a comma index to output the digital data in units of data frames according to the determined frame boundary, a decision feedback equalizer configured to process a data frame output from the first-in-first-out buffer through a decision feedback equalization operation, wherein feedback data used in the decision feedback equalization operation of the data frame uses a predetermined fixed pattern, and a comma detector configured to generate the comma index by comparing a determined value of the data frame with the predetermined fixed pattern. The data frame may include a preceding data field in which a message is stored and a subsequent comma field having the same bit value as the fixed pattern.

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