公开(公告)号：US11683934B2

公开(公告)日：2023-06-20

申请号：US17360013

申请日：2021-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  Bong Tae Park ,  Ho Jun Seong

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L23/5226 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US11626420B2

公开(公告)日：2023-04-11

申请号：US17178495

申请日：2021-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

公开(公告)号：US10770473B2

公开(公告)日：2020-09-08

申请号：US16122037

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US11864382B2

公开(公告)日：2024-01-02

申请号：US17073786

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwon Kim ,  Young-Jin Jung

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H10B43/40 ,  H01L29/792

CPC classification number: H10B43/27 ,  H01L29/7926 ,  H10B41/27 ,  H10B41/40 ,  H10B41/50 ,  H10B43/50 ,  H10B43/40

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

公开(公告)号：US20210202520A1

公开(公告)日：2021-07-01

申请号：US17178495

申请日：2021-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.

公开(公告)号：US12127408B2

公开(公告)日：2024-10-22

申请号：US18312782

申请日：2023-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  Bong Tae Park ,  Ho Jun Seong

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/40 ,  H10B43/50

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US20210074724A1

公开(公告)日：2021-03-11

申请号：US17073786

申请日：2020-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGWON KIM ,  Young-Jin Jung

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/792 ,  H01L27/11526 ,  H01L27/11575 ,  H01L27/11548

Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.

公开(公告)号：US11411024B2

公开(公告)日：2022-08-09

申请号：US16995084

申请日：2020-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US11081499B2

公开(公告)日：2021-08-03

申请号：US16818294

申请日：2020-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Jin Jung ,  Bong Tae Park ,  Ho Jun Seong

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528

Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.

公开(公告)号：US10957708B2

公开(公告)日：2021-03-23

申请号：US16520979

申请日：2019-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Young-Jin Jung ,  So-Ra Kim ,  Bong-Tae Park

IPC: H01L29/76 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00 ,  H01L23/535

Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.