公开(公告)号：US11062784B2

公开(公告)日：2021-07-13

申请号：US16844317

申请日：2020-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  H01L27/1157

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US10147739B2

公开(公告)日：2018-12-04

申请号：US15591659

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang

IPC: H01L27/11582 ,  H01L27/11578 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/768 ,  H01L29/66 ,  G11C16/04

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US20170243885A1

公开(公告)日：2017-08-24

申请号：US15591659

申请日：2017-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang

IPC: H01L27/11582 ,  H01L21/285 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L27/11582 ,  G11C16/0483 ,  H01L21/265 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/768 ,  H01L27/11578 ,  H01L29/6656

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US09711188B2

公开(公告)日：2017-07-18

申请号：US15141967

申请日：2016-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Min Hwang ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Sun-Il Shim ,  Jae-Hun Jeong ,  Ki-Hyun Kim

IPC: H01L27/112 ,  G11C5/06 ,  H01L27/115 ,  H01L27/11517

CPC classification number: G11C5/06 ,  H01L23/5283 ,  H01L27/112 ,  H01L27/115 ,  H01L27/11517

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

公开(公告)号：US10770473B2

公开(公告)日：2020-09-08

申请号：US16122037

申请日：2018-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Yun Lee ,  Jae-Hoon Jang ,  Jae-Duk Lee ,  Joon-Hee Lee ,  Young-Jin Jung

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/768 ,  H01L21/308 ,  H01L21/28 ,  H01L27/11565

Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.

公开(公告)号：US20190074292A1

公开(公告)日：2019-03-07

申请号：US16177566

申请日：2018-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-MIN HWANG ,  Han-Soo Kim ,  Won-Seok Cho ,  Jae-Hoon Jang

IPC: H01L27/11582 ,  H01L29/66 ,  H01L27/11578 ,  H01L21/768 ,  H01L21/306 ,  H01L21/285 ,  H01L21/265 ,  G11C16/04

Abstract: Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units.

公开(公告)号：US08964476B2

公开(公告)日：2015-02-24

申请号：US13867716

申请日：2013-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/115 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H01L27/1157 ,  H01L27/11582

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

Abstract translation: 非易失性存储器件，其操作方法和包括该非易失性存储器件的存储器系统。 非易失性存储器件可以包括存储单元阵列和字线驱动器。 存储单元阵列可以包括多个存储单元。 字线驱动器可以被配置为分别将字线电压施加到连接到多个存储器单元的多个字线。 字线电压的大小可以根据多个字线的位置来确定。

公开(公告)号：US11715537B2

公开(公告)日：2023-08-01

申请号：US17542183

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Il Shim ,  Jae-Hoon Jang ,  Donghyuk Chae ,  Youngho Lim ,  Hansoo Kim ,  Jaehun Jeong

IPC: G11C16/34 ,  G11C16/04 ,  H10B43/27 ,  G11C16/08 ,  G11C16/12 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  H10B43/35

CPC classification number: G11C16/3459 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4096 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  H10B43/27 ,  H10B43/35

Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.

公开(公告)号：US11031411B2

公开(公告)日：2021-06-08

申请号：US16505266

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US10978464B2

公开(公告)日：2021-04-13

申请号：US15931869

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.