公开(公告)号：US09847113B2

公开(公告)日：2017-12-19

申请号：US15258672

申请日：2016-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-dae Choi ,  Young-kwon Jo

IPC: G11C8/18 ,  G11C7/00 ,  G11C7/22 ,  G11C11/4076 ,  H03L7/081 ,  H03K5/14 ,  H03K5/00 ,  G11C29/02

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0816

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

公开(公告)号：US10283176B2

公开(公告)日：2019-05-07

申请号：US15812420

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-dae Choi ,  Young-kwon Jo

IPC: G11C8/18 ,  G11C7/00 ,  G11C8/00 ,  G11C7/22 ,  G11C11/4076 ,  H03K5/14 ,  H03L7/081 ,  G11C7/10 ,  G11C11/4093 ,  G11C29/02 ,  H03K5/00

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

公开(公告)号：US20170125077A1

公开(公告)日：2017-05-04

申请号：US15258672

申请日：2016-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-dae Choi ,  Young-kwon Jo

IPC: G11C7/22 ,  H03K5/14 ,  H03L7/081

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0816

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

公开(公告)号：US20180068699A1

公开(公告)日：2018-03-08

申请号：US15812420

申请日：2017-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-dae Choi ,  Young-kwon Jo

IPC: G11C7/22 ,  H03L7/081 ,  H03K5/14 ,  G11C8/18 ,  G11C29/02 ,  G11C11/4076 ,  H03K5/00

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/023 ,  H03K5/14 ,  H03K2005/00019 ,  H03L7/0812 ,  H03L7/0816

Abstract: Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.

公开(公告)号：US09858983B2

公开(公告)日：2018-01-02

申请号：US15220744

申请日：2016-07-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Han-gi Jung ,  Young-kwon Jo

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4076 ,  G11C7/22

CPC classification number: G11C11/4093 ,  G11C7/227 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2272 ,  G11C2207/229

Abstract: A memory device may include a latency control circuit configured to control a write latency and a read latency. The memory device compensates a write latency corresponding to a write command in response to a clock signal for a delay time on a data input path, and generates a write latency control signal. Write data input to a data bus in response to the write latency control signal is immediately aligned with the clock signal and latched and provided to a memory cell array.