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公开(公告)号：US20180068699A1
公开(公告)日：2018-03-08
申请号：US15812420
申请日：2017-11-14
发明人： Hun-dae Choi , Young-kwon Jo
CPC分类号： G11C7/222 , G11C7/1066 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C29/023 , H03K5/14 , H03K2005/00019 , H03L7/0812 , H03L7/0816
摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
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公开(公告)号：US09847113B2
公开(公告)日：2017-12-19
申请号：US15258672
申请日：2016-09-07
发明人： Hun-dae Choi , Young-kwon Jo
CPC分类号： G11C7/222 , G11C7/1066 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C29/023 , H03K5/14 , H03K2005/00019 , H03L7/0812 , H03L7/0816
摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
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公开(公告)号：US10276220B2
公开(公告)日：2019-04-30
申请号：US15674250
申请日：2017-08-10
发明人： Juho Jeon , Hun-dae Choi
IPC分类号： G11C7/10 , H01L25/065 , G11C29/02
摘要： A memory device configured to perform a ZQ calibration method may include a first die and a second die that share a resistor connected to a ZQ pin. The first die may be configured to perform a first calibration operation using the resistor in response to a ZQ calibration command applied from outside of the memory device. The first die may be configured to generate a ZQ flag signal after the first calibration operation ends and perform a second calibration operation. The second die may be configured to perform the first calibration operation in response to the ZQ flag signal and perform a second calibration after the first calibration operation of the second die ends.
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公开(公告)号：US20190140628A1
公开(公告)日：2019-05-09
申请号：US16026145
申请日：2018-07-03
发明人： WANGSOO KIM , Hangi Jung , Kiduk Park , Yoo-Chang Sung , Jae-Hun Jung , Cheongryong Cho , Hun-dae Choi
IPC分类号： H03K5/13
CPC分类号： H03K5/13 , H03K2005/00019 , H04B1/04
摘要： An electronic circuit may include a driver, a delay circuit, a strength control circuit, and an adder circuit. The driver may generate a second signal based on a first signal. The delay circuit may delay the first signal by as much as a reference time, to generate a third signal. The strength control circuit may adjust an amplitude of the third signal to generate a fourth signal. The adder circuit may add the second signal and the fourth signal to generate a fifth signal. In a first time interval determined based on the reference time, an amplitude of the fifth signal may be greater than an amplitude of the second signal. In a second time interval except for the first time interval, the amplitude of the fifth signal may be smaller than the amplitude of the second signal. In the second time interval, the amplitude of the fifth signal may be smaller than an amplitude of the first signal.
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公开(公告)号：US10283176B2
公开(公告)日：2019-05-07
申请号：US15812420
申请日：2017-11-14
发明人： Hun-dae Choi , Young-kwon Jo
IPC分类号： G11C8/18 , G11C7/00 , G11C8/00 , G11C7/22 , G11C11/4076 , H03K5/14 , H03L7/081 , G11C7/10 , G11C11/4093 , G11C29/02 , H03K5/00
摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
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公开(公告)号：US20170125077A1
公开(公告)日：2017-05-04
申请号：US15258672
申请日：2016-09-07
发明人： Hun-dae Choi , Young-kwon Jo
CPC分类号： G11C7/222 , G11C7/1066 , G11C8/18 , G11C11/4076 , G11C11/4093 , G11C29/023 , H03K5/14 , H03K2005/00019 , H03L7/0812 , H03L7/0816
摘要： Provided is a delay-locked loop circuit for providing a delay-locked clock signal to a data output buffer, the delay-locked loop circuit including: a first delay-locked-mode-based selector configured to select, as a first selected clock signal, one of a first divided clock signal, which is obtained by dividing a reference clock signal by N, and the reference clock signal; and a delay-locked mode controller configured to determine a delay-locked mode on the basis of a command received from the outside and to control the first delay-locked-mode-based selector according to the delay-locked mode. The delay-locked clock signal is generated by comparing a phase of a feedback clock signal generated from the first selected clock signal with a phase of the reference clock signal.
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