公开(公告)号：US20240223187A1

公开(公告)日：2024-07-04

申请号：US18381611

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younggyu Lee ,  TONGSUNG KIM ,  SEUNGJUN BAE ,  SEONKYOO LEE ,  TAESUNG LEE

IPC: H03K19/00 ,  H03K19/017 ,  H03K19/17784

CPC classification number: H03K19/0005 ,  H03K19/01721 ,  H03K19/17784

Abstract: A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.

公开(公告)号：US20250095755A1

公开(公告)日：2025-03-20

申请号：US18932736

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C29/02

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal from the memory controller, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command signal received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate first to fourth clock signals having different phases from each other based on the data strobe signal, and perform a write duty cycle correct operation to correct a duty cycle for the first clock signal and the third clock signal which have a phase difference of 180° and to correct a duty cycle for the second clock signal and the fourth clock signal which have a phase difference of 180°, wherein the read duty cycle correct operation and the write duty cycle correct operation are performed simultaneously.

公开(公告)号：US20250095754A1

公开(公告)日：2025-03-20

申请号：US18804617

申请日：2024-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Seonkyoo Lee ,  Younggyu Lee ,  Taesung Lee

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  H03K5/156

Abstract: Provided is a memory device including a first pad configured to receive a read enable signal from a memory controller, a second pad configured to receive a read duty cycle correct command signal, a first duty correction circuit configured to perform a read duty cycle correct operation, based on the read duty cycle correct command received from the memory controller, when the read enable signal is received, and output a data strobe signal generated based on the read duty cycle correct operation, and a second duty correction circuit configured to receive the data strobe signal from the first duty correction circuit, generate a divided data strobe signal by dividing the received data strobe signal, and compare the received data strobe signal with the divided data strobe signal to perform a write duty cycle correct operation.